Re: [PATCH] RISC-V: Don't enable all interrupts in trap_init()

[Atish Patra]

On Sun, Feb 2, 2020 at 3:06 AM Anup Patel <anup.patel@xxxxxxx> wrote:
>
> Historically, we have been enabling all interrupts for each
> HART in trap_init(). Ideally, we should only enable M-mode
> interrupts for M-mode kernel and S-mode interrupts for S-mode
> kernel in trap_init().
>
> Currently, we get suprious S-mode interrupts on Kendryte K210
> board running M-mode NO-MMU kernel because we are enabling all
> interrupts in trap_init(). To fix this, we only enable software
> and external interrupt in trap_init(). In future, trap_init()
> will only enable software interrupt and PLIC driver will enable
> external interrupt using CPU notifiers.
>
> Cc: stable@xxxxxxxxxxxxxxx
> Fixes: 76d2a0493a17 ("RISC-V: Init and Halt Code)
> Signed-off-by: Anup Patel <anup.patel@xxxxxxx>
> ---
>  arch/riscv/kernel/traps.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c
> index f4cad5163bf2..ffb3d94bf0cc 100644
> --- a/arch/riscv/kernel/traps.c
> +++ b/arch/riscv/kernel/traps.c
> @@ -156,6 +156,6 @@ void __init trap_init(void)
>         csr_write(CSR_SCRATCH, 0);
>         /* Set the exception vector address */
>         csr_write(CSR_TVEC, &handle_exception);
> -       /* Enable all interrupts */
> -       csr_write(CSR_IE, -1);
> +       /* Enable interrupts */
> +       csr_write(CSR_IE, IE_SIE | IE_EIE);
>  }
> --
> 2.17.1
>
>

Looks good.
Reviewed-by: Atish Patra <atish.patra@xxxxxxx>
-- 
Regards,
Atish