Re: [PATCH v3 4/4] phy: qcom-qmp: Use proper PWRDOWN offset for sm8150 USB

[Wesley Cheng]

On 3/25/2020 10:43 AM, Wesley Cheng wrote:
> The register map for SM8150 QMP USB SSPHY has moved
> QPHY_POWER_DOWN_CONTROL to a different offset.  Allow for
> an offset in the register table to override default value
> if it is a DP capable PHY.
> 
> Signed-off-by: Wesley Cheng <wcheng@xxxxxxxxxxxxxx>
> ---
>  drivers/phy/qualcomm/phy-qcom-qmp.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
> index cc04471..71a230a 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
> @@ -164,6 +164,7 @@ enum qphy_reg_layout {
>  	[QPHY_SW_RESET]			= 0x00,
>  	[QPHY_START_CTRL]		= 0x44,
>  	[QPHY_PCS_STATUS]		= 0x14,
> +	[QPHY_COM_POWER_DOWN_CONTROL]	= 0x40,
>  };
>  
>  static const unsigned int sdm845_ufsphy_regs_layout[] = {
> @@ -1627,6 +1628,9 @@ static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
>  	if (cfg->has_phy_com_ctrl)
>  		qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
>  			     SW_PWRDN);
> +	else if (!cfg->has_phy_com_ctrl && cfg->regs[QPHY_COM_POWER_DOWN_CONTROL])
> +		qphy_setbits(pcs, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
> +			     cfg->pwrdn_ctrl);
>  	else
>  		qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
>  
> 

Will add logic to the qcom_qmp_phy_com_exit() API as well to fix the
power down offset if DP com is being used, and will check for
has_phy_dp_com_ctrl instead of !has_phy_com_ctrl, as to ensure this only
applies to PHYs that have DP COM.

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