RE: [PATCH] serial: sh-sci: Make sure status register SCxSR is read in correct sequence

[Chris Brandt]

Hi Geert,

On Tue, Mar 31, 2020 1, Geert Uytterhoeven wrote:
> However, the documentation for "SCIFA" on RZ/A2 (for which we use
> PORT_SCIF, not PORT_SCIFA, in the driver) has conflicting information:
>   1. Section 17.2.7 "Serial Status Register (FSR)" says:
>        - A receive framing/parity error occurred in the "next receive
>          data read" from the FIFO,
>        - Indicates whether there is a framing/parity error in the data
>          "read" from the FIFO.
>   2. Figure 17.8 "Sample Flowchart for Receiving Serial Data in
>      Asynchronous Mode (2)".
>        - Whether a framing error or parity error has occurred in the
>          received data that is "read" from the FIFO.
> 
> So while the change looks OK for most Renesas ARM SoCs, the situation
> for RZ/A2 is unclear.
> Note that the above does not take into account variants used on SuperH
> SoCs.

For the RZ/A2M, it is NOT a "SCIFA"...even though it says that in the 
hardware manual.

And honestly, I could not trace back where that IP came from. It was 
from somewhere in the MCU design section (not the SoC design section). 
Someone modified the IP so they put an "A" at the end to show it was 
different. Regardless, it has a different history than all the other IP 
supported by the SCI driver.

Chris