Re: [RFC PATCH 5/7] riscv: Use pgtable_l4_enabled to output mmu type in cpuinfo

From: Alex Ghiti
Date: Tue Apr 07 2020 - 01:14:34 EST




On 4/3/20 11:53 AM, Palmer Dabbelt wrote:
On Sun, 22 Mar 2020 04:00:26 PDT (-0700), alex@xxxxxxxx wrote:
Now that the mmu type is determined at runtime using SATP
characteristic, use the global variable pgtable_l4_enabled to output
mmu type of the processor through /proc/cpuinfo instead of relying on
device tree infos.

Signed-off-by: Alexandre Ghiti <alex@xxxxxxxx>
---
Âarch/riscv/boot/dts/sifive/fu540-c000.dtsi |Â 4 ----
Âarch/riscv/kernel/cpu.cÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ | 24 ++++++++++++----------
Â2 files changed, 13 insertions(+), 15 deletions(-)

diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
index 7db861053483..6138590a2229 100644
--- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
@@ -50,7 +50,6 @@
ÂÂÂÂÂÂÂÂÂÂÂÂ i-cache-size = <32768>;
ÂÂÂÂÂÂÂÂÂÂÂÂ i-tlb-sets = <1>;
ÂÂÂÂÂÂÂÂÂÂÂÂ i-tlb-size = <32>;
-ÂÂÂÂÂÂÂÂÂÂÂ mmu-type = "riscv,sv39";
ÂÂÂÂÂÂÂÂÂÂÂÂ reg = <1>;
ÂÂÂÂÂÂÂÂÂÂÂÂ riscv,isa = "rv64imafdc";
ÂÂÂÂÂÂÂÂÂÂÂÂ tlb-split;
@@ -74,7 +73,6 @@
ÂÂÂÂÂÂÂÂÂÂÂÂ i-cache-size = <32768>;
ÂÂÂÂÂÂÂÂÂÂÂÂ i-tlb-sets = <1>;
ÂÂÂÂÂÂÂÂÂÂÂÂ i-tlb-size = <32>;
-ÂÂÂÂÂÂÂÂÂÂÂ mmu-type = "riscv,sv39";
ÂÂÂÂÂÂÂÂÂÂÂÂ reg = <2>;
ÂÂÂÂÂÂÂÂÂÂÂÂ riscv,isa = "rv64imafdc";
ÂÂÂÂÂÂÂÂÂÂÂÂ tlb-split;
@@ -98,7 +96,6 @@
ÂÂÂÂÂÂÂÂÂÂÂÂ i-cache-size = <32768>;
ÂÂÂÂÂÂÂÂÂÂÂÂ i-tlb-sets = <1>;
ÂÂÂÂÂÂÂÂÂÂÂÂ i-tlb-size = <32>;
-ÂÂÂÂÂÂÂÂÂÂÂ mmu-type = "riscv,sv39";
ÂÂÂÂÂÂÂÂÂÂÂÂ reg = <3>;
ÂÂÂÂÂÂÂÂÂÂÂÂ riscv,isa = "rv64imafdc";
ÂÂÂÂÂÂÂÂÂÂÂÂ tlb-split;
@@ -122,7 +119,6 @@
ÂÂÂÂÂÂÂÂÂÂÂÂ i-cache-size = <32768>;
ÂÂÂÂÂÂÂÂÂÂÂÂ i-tlb-sets = <1>;
ÂÂÂÂÂÂÂÂÂÂÂÂ i-tlb-size = <32>;
-ÂÂÂÂÂÂÂÂÂÂÂ mmu-type = "riscv,sv39";
ÂÂÂÂÂÂÂÂÂÂÂÂ reg = <4>;
ÂÂÂÂÂÂÂÂÂÂÂÂ riscv,isa = "rv64imafdc";
ÂÂÂÂÂÂÂÂÂÂÂÂ tlb-split;
diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index 40a3c442ac5f..38a699b997a8 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -8,6 +8,8 @@
Â#include <linux/of.h>
Â#include <asm/smp.h>

+extern bool pgtable_l4_enabled;
+
Â/*
 * Returns the hart ID of the given device tree node, or -ENODEV if the node
 * isn't an enabled and valid RISC-V hart node.
@@ -54,18 +56,19 @@ static void print_isa(struct seq_file *f, const char *isa)
ÂÂÂÂ seq_puts(f, "\n");
Â}

-static void print_mmu(struct seq_file *f, const char *mmu_type)
+static void print_mmu(struct seq_file *f)
Â{
+ÂÂÂ char sv_type[16];
+
Â#if defined(CONFIG_32BIT)
-ÂÂÂ if (strcmp(mmu_type, "riscv,sv32") != 0)
-ÂÂÂÂÂÂÂ return;
+ÂÂÂ strncpy(sv_type, "sv32", 5);
Â#elif defined(CONFIG_64BIT)
-ÂÂÂ if (strcmp(mmu_type, "riscv,sv39") != 0 &&
-ÂÂÂÂÂÂÂ strcmp(mmu_type, "riscv,sv48") != 0)
-ÂÂÂÂÂÂÂ return;
+ÂÂÂ if (pgtable_l4_enabled)
+ÂÂÂÂÂÂÂ strncpy(sv_type, "sv48", 5);
+ÂÂÂ else
+ÂÂÂÂÂÂÂ strncpy(sv_type, "sv39", 5);
Â#endif
-
-ÂÂÂ seq_printf(f, "mmu\t\t: %s\n", mmu_type+6);
+ÂÂÂ seq_printf(f, "mmu\t\t: %s\n", sv_type);
Â}

Âstatic void *c_start(struct seq_file *m, loff_t *pos)
@@ -90,14 +93,13 @@ static int c_show(struct seq_file *m, void *v)
Â{
ÂÂÂÂ unsigned long cpu_id = (unsigned long)v - 1;
ÂÂÂÂ struct device_node *node = of_get_cpu_node(cpu_id, NULL);
-ÂÂÂ const char *compat, *isa, *mmu;
+ÂÂÂ const char *compat, *isa;

ÂÂÂÂ seq_printf(m, "processor\t: %lu\n", cpu_id);
ÂÂÂÂ seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id));
ÂÂÂÂ if (!of_property_read_string(node, "riscv,isa", &isa))
ÂÂÂÂÂÂÂÂ print_isa(m, isa);
-ÂÂÂ if (!of_property_read_string(node, "mmu-type", &mmu))
-ÂÂÂÂÂÂÂ print_mmu(m, mmu);
+ÂÂÂ print_mmu(m);
ÂÂÂÂ if (!of_property_read_string(node, "compatible", &compat)
ÂÂÂÂÂÂÂÂ && strcmp(compat, "riscv"))
ÂÂÂÂÂÂÂÂ seq_printf(m, "uarch\t\t: %s\n", compat);

Reviewed-by: Palmer Dabbelt <palmerdabbelt@xxxxxxxxxx>

Thanks,

Alex