Re: [RFC PATCH 6/7] dt-bindings: riscv: Remove "riscv,svXX" property from device-tree

[Alex Ghiti]

On 4/3/20 11:53 AM, Palmer Dabbelt wrote:
> On Sun, 22 Mar 2020 04:00:27 PDT (-0700), alex@xxxxxxxx wrote:
> > This property can not be used before virtual memory is set up
> > and then the distinction between sv39 and sv48 is done at runtime
> > using SATP csr property: this property is now useless, so remove it.
> >
> > Signed-off-by: Alexandre Ghiti <alex@xxxxxxxx>
> > ---
> > ÂDocumentation/devicetree/bindings/riscv/cpus.yaml | 13 -------------
> > Â1 file changed, 13 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml 
> > b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > index 04819ad379c2..12baabbac213 100644
> > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > @@ -39,19 +39,6 @@ properties:
> > ÂÂÂÂÂÂ Identifies that the hart uses the RISC-V instruction set
> > ÂÂÂÂÂÂ and identifies the type of the hart.
> >
> > -Â mmu-type:
> > -ÂÂÂ allOf:
> > -ÂÂÂÂÂ - $ref: "/schemas/types.yaml#/definitions/string"
> > -ÂÂÂÂÂ - enum:
> > -ÂÂÂÂÂÂÂÂÂ - riscv,sv32
> > -ÂÂÂÂÂÂÂÂÂ - riscv,sv39
> > -ÂÂÂÂÂÂÂÂÂ - riscv,sv48
> > -ÂÂÂ description:
> > -ÂÂÂÂÂ Identifies the MMU address translation mode used on this
> > - hart. These values originate from the RISC-V Privileged
> > -ÂÂÂÂÂ Specification document, available from
> > -ÂÂÂÂÂ https://riscv.org/specifications/
> > -
> > ÂÂ riscv,isa:
> > ÂÂÂÂ allOf:
> > ÂÂÂÂÂÂ - $ref: "/schemas/types.yaml#/definitions/string"
>
> I'd prefer if we continue to define this in the schema: while Linux 
> won't use
> it, it's still useful for other programs that want to statically 
> determine the
> available VA widths.

Sure, I'll remove that in next version.

Thanks,

Alex