Hi Mike,
Thanks for taking a look.
On 2020-04-06 16:25, Mike Leach wrote:
Hi,
The programmable replicator hardware by design enables trace through
both ports on reset. (see 1, section 4.4, 9.11)Â The replicator driver
overrides this functionality to disable output, until the Coresight
infrastructure chooses a path from source to sink.
Now given that the hardware design is such that we must be able to
allow trace to be sent to both ports, a generic patch to prevent this
does not seem appropriate here.
I think this needs further investigation - to determine why this
appears to be failing in this particular instance.
Yes, this probably needs further investigation, but CPU hardlock stack
trace doesnt help much. I could always trigger this hard lockup without
this patch on SC7180 SoC and this is only seen when ETR is used as the sink.
The only difference I could see between non working case (on SC7180 [1]) and
the working case (on SDM845 [2]) is the path from source to sink.
SC7180 source to sink path(Not working):
----------------------------------------
ÂÂÂÂÂ etm0_out
ÂÂÂÂ |
 apss_funnel_in0
ÂÂÂÂÂÂÂÂ |
Âapss_merge_funnel_in
ÂÂÂÂÂÂÂÂ |
ÂÂÂÂ funnel1_in4
ÂÂÂÂ |
 merge_funnel_in1
ÂÂÂÂ |
ÂÂ swao_funnel_in
ÂÂÂÂÂÂÂÂ |
ÂÂÂÂÂÂ etf_in
ÂÂÂÂ |
Âswao_replicator_in
ÂÂÂÂÂÂÂÂ |
 replicator_in
ÂÂÂÂ |
ÂÂÂÂÂÂ etr_in