Re: [PATCH v3 1/4] dt-bindings: phy: Add binding for qcom,usb-hs-7nm

[Stephen Boyd]

Quoting Wesley Cheng (2020-04-07 15:23:26)
> diff --git a/Documentation/devicetree/bindings/phy/qcom,usb-hs-7nm.yaml b/Documentation/devicetree/bindings/phy/qcom,usb-hs-7nm.yaml
> new file mode 100644
> index 0000000..7292e27
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/qcom,usb-hs-7nm.yaml
> @@ -0,0 +1,76 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/phy/qcom,usb-hs-7nm.yaml#";
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#";
> +
> +title: Qualcomm Synopsys 7nm High-Speed USB PHY
> +
> +maintainers:
> +  - Wesley Cheng <wcheng@xxxxxxxxxxxxxx>
> +
> +description: |
> +  Qualcomm Hi-Speed 7nm USB PHY

High?

> +
> +properties:
> +  compatible:
> +    enum:
> +      - qcom,usb-snps-hs-7nm-phy
> +      - qcom,sm8150-usb-hs-phy
> +
> +  reg:
> +    maxItems: 1
> +
> +  "#phy-cells":
> +    const: 0
> +
> +  clocks:
> +    items:
> +      - description: rpmhcc ref clock
> +
> +  clock-names:
> +    items:
> +      - const: ref
> +
> +  resets:
> +    items:
> +      - description: PHY core reset
> +
> +  vdda-pll-supply:
> +    description: phandle to the regulator VDD supply node.
> +
> +  vdda18-supply:
> +    description: phandle to the regulator 1.8V supply node.
> +
> +  vdda33-supply:
> +    description: phandle to the regulator 3.3V supply node.
> +
> +required:
> +  - compatible
> +  - reg
> +  - "#phy-cells"
> +  - clocks
> +  - clock-names
> +  - resets
> +  - vdda-pll-supply
> +  - vdda18-supply
> +  - vdda33-supply
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/qcom,rpmh.h>
> +    #include <dt-bindings/clock/qcom,gcc-sm8150.h>
> +    usb_1_hsphy: phy@88e2000 {

Is the label necessary? Best to drop it if not.

> +        compatible = "qcom,sm8150-usb-hs-phy";
> +        reg = <0 0x088e2000 0 0x400>;
> +        status = "disabled";

I think we can leave out status in examples.

> +        #phy-cells = <0>;
> +
> +        clocks = <&rpmhcc RPMH_CXO_CLK>;
> +        clock-names = "ref";
> +
> +        resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
> +    };
> +...
> \ No newline at end of file

Why no newline at end of file?

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