Re: [PATCH v2 00/11] perf c2c: Sort cacheline with all loads

[Jiri Olsa]

On Mon, Jan 04, 2021 at 10:09:38AM +0800, Leo Yan wrote:

SNIP

> > > Leo Yan (11):
> > >   perf c2c: Add dimensions for total load hit
> > >   perf c2c: Add dimensions for load hit
> > >   perf c2c: Add dimensions for load miss
> > >   perf c2c: Rename for shared cache line stats
> > >   perf c2c: Refactor hist entry validation
> > >   perf c2c: Refactor display filter macro
> > >   perf c2c: Refactor node display macro
> > >   perf c2c: Refactor node header
> > >   perf c2c: Add local variables for output metrics
> > >   perf c2c: Sort on all cache hit for load operations
> > >   perf c2c: Update documentation for display option 'all'
> > > 
> > >  tools/perf/Documentation/perf-c2c.txt |  21 +-
> > >  tools/perf/builtin-c2c.c              | 548 ++++++++++++++++++++++----
> > >  2 files changed, 487 insertions(+), 82 deletions(-)
> > 
> > Joe might want to test it first, but it looks all good to me:
> > 
> > Acked-by: Jiri Olsa <jolsa@xxxxxxxxxx>
> 
> Thanks for the review, Jiri.
> 
> Note, after testing with Arm SPE, we found the store operations don't
> contain the information for L1 cache hit or miss, this leads to there
> have no statistics for "st_l1hit" and "st_l1miss"; finally the single
> cache line view only can show the load samples and fails to show store
> opreations due to the empty statistics for "st_l1hit" and "st_l1miss".
> 
> This is related the hardware issue, after some discussion internally,
> so far cannot find a easy way to set memory flag for L1 cache hit or
> miss for store operations (more specific, set flags PERF_MEM_LVL_HIT or
> PERF_MEM_LVL_MISS for store's L1 cache accessing).
> 
> Given it is uncertain for this issue, please hold on for this patch
> series and I will resend if have any conclusion.
> 
> And really sorry I notify this too late.

no problem, I think we can take some of the refactoring patches anyway

thanks,
jirka