[PATCH v1 07/20] ASoC: tegra20: spdif: Set FIFO trigger level
From: Dmitry Osipenko
Date: Wed Nov 24 2021 - 17:06:48 EST
Program FIFO trigger level properly to fix x4 accelerated playback.
Signed-off-by: Dmitry Osipenko <digetx@xxxxxxxxx>
---
sound/soc/tegra/tegra20_spdif.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/sound/soc/tegra/tegra20_spdif.c b/sound/soc/tegra/tegra20_spdif.c
index bd81df5378d1..6650875d2555 100644
--- a/sound/soc/tegra/tegra20_spdif.c
+++ b/sound/soc/tegra/tegra20_spdif.c
@@ -70,6 +70,14 @@ static int tegra20_spdif_hw_params(struct snd_pcm_substream *substream,
regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_CTRL, mask, val);
+ /*
+ * FIFO trigger level must be bigger than DMA burst or equal to it,
+ * otherwise data is discarded on overflow.
+ */
+ regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_DATA_FIFO_CSR,
+ TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_MASK,
+ TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_TU4_WORD_FULL);
+
switch (params_rate(params)) {
case 32000:
spdifclock = 4096000;
--
2.33.1