RE: [PATCH v2 2/2] net: ethernet: Add driver for Sunplus SP7021

[Wells Lu 呂芳騰]

Hi Andrew,

I read specification of ICPlus IP101G (10M/100M PHY).
Bits of register 0 (control) and register 1 (status) 
are R/W or RO type. They will not be cleared after 
read. No matter how many times they are read, the 
read-back value is the same.

For example,
Value of register 0 (control) is 0x3100
Value of register 1 (status) is 0x786d 

The read-back values are always the same unless you 
unplug the cable.

Besides, we use polling mode (phydev->irq = PHY_POLL) 
PHY state-machine is triggered by using 1-Hz work-
queue, not interrupt.

We didn't find any problem after many tests after 
using 'force' mode.

Can we go with this approach?


Best regards,
Wells


> > Hi Andrew,
> >
> >
> > From data provided by ASIC engineer, MAC of SP7021 only reads the 4
> > registers of PHY:
> > 0: Control register
> > 1: Status register
> 
> This is the register which has latching of the link status. genphy_update_link() expects
> this latching behaviour, and if the hardware reads the register, that behaviour is not
> going to happen.
> 
> 	Andrew