Re: [PATCH V4 1/2] dt-bindings: riscv: add MMU Standard Extensions support for Svpbmt

[Philipp Tomsich]

We did touch on this in our coordination call a few weeks ago: the
grouping under mmu and the bool-entries were chosen because of their
similarity to other extensions (i.e. for Zb[abcs] there could/should
be a bool-entry under each cpu-node — for some Zv* entries a subnode
might be needed with further parameters).

The string-based approach (as in the originally proposed "mmu-type=")
would like not scale with the proliferation of small & modular
extensions.

Philipp.


On Tue, 30 Nov 2021 at 14:59, Jessica Clarke <jrtc27@xxxxxxxxxx> wrote:
>
> On 30 Nov 2021, at 13:27, Heiko Stübner <heiko@xxxxxxxxx> wrote:
> >
> > Hi,
> >
> > Am Dienstag, 30. November 2021, 14:17:41 CET schrieb Jessica Clarke:
> >> On 30 Nov 2021, at 12:07, Heiko Stübner <heiko@xxxxxxxxx> wrote:
> >>>
> >>> Am Montag, 29. November 2021, 13:06:23 CET schrieb Heiko Stübner:
> >>>> Am Montag, 29. November 2021, 09:54:39 CET schrieb Heinrich Schuchardt:
> >>>>> On 11/29/21 02:40, wefu@xxxxxxxxxx wrote:
> >>>>>> From: Wei Fu <wefu@xxxxxxxxxx>
> >>>>>>
> >>>>>> Previous patch has added svpbmt in arch/riscv and add "riscv,svpmbt"
> >>>>>> in the DT mmu node. Update dt-bindings related property here.
> >>>>>>
> >>>>>> Signed-off-by: Wei Fu <wefu@xxxxxxxxxx>
> >>>>>> Co-developed-by: Guo Ren <guoren@xxxxxxxxxx>
> >>>>>> Signed-off-by: Guo Ren <guoren@xxxxxxxxxx>
> >>>>>> Cc: Anup Patel <anup@xxxxxxxxxxxxxx>
> >>>>>> Cc: Palmer Dabbelt <palmer@xxxxxxxxxxx>
> >>>>>> Cc: Rob Herring <robh+dt@xxxxxxxxxx>
> >>>>>> ---
> >>>>>> Documentation/devicetree/bindings/riscv/cpus.yaml | 10 ++++++++++
> >>>>>> 1 file changed, 10 insertions(+)
> >>>>>>
> >>>>>> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> >>>>>> index aa5fb64d57eb..9ff9cbdd8a85 100644
> >>>>>> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> >>>>>> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> >>>>>> @@ -63,6 +63,16 @@ properties:
> >>>>>>       - riscv,sv48
> >>>>>>       - riscv,none
> >>>>>>
> >>>>>> +  mmu:
> >>>>>
> >>>>> Shouldn't we keep the items be in alphabetic order, i.e. mmu before
> >>>>> mmu-type?
> >>>>>
> >>>>>> +    description:
> >>>>>> +      Describes the CPU's MMU Standard Extensions support.
> >>>>>> +      These values originate from the RISC-V Privileged
> >>>>>> +      Specification document, available from
> >>>>>> +      https://riscv.org/specifications/
> >>>>>> +    $ref: '/schemas/types.yaml#/definitions/string'
> >>>>>> +    enum:
> >>>>>> +      - riscv,svpmbt
> >>>>>
> >>>>> The privileged specification has multiple MMU related extensions:
> >>>>> Svnapot, Svpbmt, Svinval. Shall they all be modeled in this enum?
> >>>>
> >>>> I remember in some earlier version some way back there was the
> >>>> suggestion of using a sub-node instead and then adding boolean
> >>>> properties for the supported extensions.
> >>>>
> >>>> Aka something like
> >>>>    mmu {
> >>>>            riscv,svpbmt;
> >>>>    };
> >>>
> >>> For the record, I'm talking about the mail from september
> >>> https://lore.kernel.org/linux-riscv/CAAeLtUChjjzG+P8yg45GLZMJy5UR2K5RRBoLFVZhtOaZ5pPtEA@xxxxxxxxxxxxxx/
> >>>
> >>> So having a sub-node would make adding future extensions
> >>> way nicer.
> >>
> >> Svpbmt is just an ISA extension, and should be treated like any other.
> >> Let’s not invent two different ways of representing that in the device
> >> tree.
> >
> > Heinrich asked how the other extensions should be handled
> > (Svnapot, Svpbmt, Svinval), so what do you suggest to do with these?
>
> Whatever is done for Zb[abcs], Zk*, Zv*, Zicbo*, etc. There may not be
> a concrete plan for that yet, but that means you should speak with the
> people involved with such extensions and come up with something
> appropriate together.
>
> Jess
>