Re: [PATCH] clk: renesas: r9a07g044: Update multiplier and divider values for PLL2/3

[Geert Uytterhoeven]

On Thu, Dec 23, 2021 at 10:32 AM Lad Prabhakar
<prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> wrote:
> As per the HW manual (Rev.1.00 Sep, 2021) PLL2 and PLL3 should be 1600MHz,
> but with current multiplier and divider values this resulted to 1596MHz.
>
> This patch updates the multiplier and divider values for PLL2 and PLL3
> so that we get the exact (1600MHz) values.
>
> Fixes: 17f0ff3d49ff1 ("clk: renesas: Add support for R9A07G044 SoC")
> Suggested-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>

Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
i.e. will queue in renesas-clk-for-v5.18.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

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