Re: [RFC PATCH 5/5] x86/entry: Store CPU info on exception entry

[Borislav Petkov]

On Mon, Aug 08, 2022 at 01:03:24PM +0200, Ingo Molnar wrote:
> I'd like to hear what Andy Lutomirski thinks about the notion that
> "2 instructions don't matter at all" ...
> 
> Especially since it's now 4 instructions:

He wasn't opposed to it when we talked on IRC last week.

> ... 4 instructions in the exception path is a non-trivial impact.

How do I measure this "impact"?

Hell, we recently added retbleed - and IBRS especially on Intel - on
the entry path which is whopping 30% perf impact in some cases. And
now we're arguing about a handful of insns. I'm sceptical they'll be
anything else but "in-the-noise" in any sensible workload.

Thx.

-- 
Regards/Gruss,
    Boris.

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