RE: [PATCH V2] dt-bindings: clock: add i.MX8M Anatop

[Peng Fan]

> Subject: Re: [PATCH V2] dt-bindings: clock: add i.MX8M Anatop
> 
> On 13/09/2022 11:29, Peng Fan (OSS) wrote:
> > From: Peng Fan <peng.fan@xxxxxxx>
> >
> > i.MX8M Family features an anatop module the produces PLL to clock
> > control module(CCM) root clock. Add the missing yaml file.
> >
> > Signed-off-by: Peng Fan <peng.fan@xxxxxxx>
> > ---
> >
> > V2:
> >  Drop syscon, use clock-controller
> >  Add fsl vendor prefix
> >  Add interrupt property
> >
> >  dts update not included, so there will be dtbs_check fail.
> >
> >  .../bindings/clock/fsl,imx8m-anatop.yaml      | 46 +++++++++++++++++++
> >  1 file changed, 46 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/clock/fsl,imx8m-anatop.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/clock/fsl,imx8m-anatop.yaml
> > b/Documentation/devicetree/bindings/clock/fsl,imx8m-anatop.yaml
> > new file mode 100644
> > index 000000000000..2c0efa58d898
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/fsl,imx8m-anatop.yaml
> > @@ -0,0 +1,46 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id:
> >
> +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> > +cetree.org%2Fschemas%2Fclock%2Ffsl%2Cimx8m-
> anatop.yaml%23&amp;data=05
> >
> +%7C01%7Cpeng.fan%40nxp.com%7Ca3a47985f9d9452744af08da9590fe79
> %7C686ea
> >
> +1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637986747221860721%7CU
> nknown%7C
> >
> +TWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWw
> iLCJXV
> >
> +CI6Mn0%3D%7C3000%7C%7C%7C&amp;sdata=I4LSaFBDMZv%2FcgFyIR1w
> m2Irc%2F%2F
> > +Z9eKChPCJY7XMfDo%3D&amp;reserved=0
> > +$schema:
> >
> +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> > +cetree.org%2Fmeta-
> schemas%2Fcore.yaml%23&amp;data=05%7C01%7Cpeng.fan%
> >
> +40nxp.com%7Ca3a47985f9d9452744af08da9590fe79%7C686ea1d3bc2b4c6
> fa92cd9
> >
> +9c5c301635%7C0%7C0%7C637986747221860721%7CUnknown%7CTWFpb
> GZsb3d8eyJWI
> >
> +joiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7
> C3000%
> >
> +7C%7C%7C&amp;sdata=dm5exAJpmPmY%2B0vCuZtpzt7k8GHeKZKtitSvep0
> 5G%2Bw%3D
> > +&amp;reserved=0
> > +
> > +title: NXP i.MX8M Family Anatop Module
> > +
> > +maintainers:
> > +  - Peng Fan <peng.fan@xxxxxxx>
> > +
> > +description: |
> > +  NXP i.MX8M Family anatop PLL module which generates PLL to CCM root.
> > +
> > +properties:
> > +  compatible:
> > +    oneOf:
> > +      - enum:
> > +          - fsl,imx8mm-anatop
> > +          - fsl,imx8mq-anatop
> > +      - items:
> > +          - enum:
> > +              - fsl,imx8mn-anatop
> > +              - fsl,imx8mp-anatop
> > +          - const: fsl,imx8mm-anatop
> 
> You dropped syscon which solves part of my previous comment. I suggested
> to make it proper clock provider, so you would need clock-cells. Any reason
> it is no a real clock provider?

oh. I overlooked this point. The current i.MX8M linux clk driver directly
search the node to get anatop base:
https://elixir.bootlin.com/linux/v6.0-rc5/source/drivers/clk/imx/clk-imx8mp.c#L416

Not take it as a real clock provider from linux view.

I will add clock-cells in v3.

Thanks,
Peng.

> 
> Best regards,
> Krzysztof