Re: [PATCHv8 00/11] Linear Address Masking enabling

[Dave Hansen]

On 9/23/22 04:46, Jason Gunthorpe wrote:
> On Fri, Sep 23, 2022 at 12:38:26PM +0300, Kirill A. Shutemov wrote:
>>> So I would assume an untagged pointer should just be fine for the IOMMU
>>> to walk. IOMMU currently wants canonical addresses for VA.
>> Right. But it means that LAM compatibility can be block on two layers:
>> IOMMU and device. IOMMU is not the only HW entity that has to be aware of
>> tagged pointers.
> Why does a device need to care about this? What do you imagine a
> device doing with it?
> 
> The userspace should program the device with the tagged address, the
> device should present the tagged address on the bus, the IOMMU should
> translate the tagged address the same as the CPU by ignoring the upper
> bits.

Is this how *every* access works?  Every single device access to the
address space goes through the IOMMU?

I thought devices also cached address translation responses from the
IOMMU and stashed them in their own device-local TLB.  If the device is
unaware of the tags, then how does device TLB invalidation work?  Would
all device TLB flushes be full flushes of the devices TLB?  If something
tried to use single-address invalidation, it would need to invalidate
every possible tag alias because the device wouldn't know that the tags
*are* tags instead of actual virtual addresses.