Re: [PATCH] x86/speculation: Mitigate eIBRS PBRSB predictions with WRMSR

[pawan.kumar.gupta@xxxxxxxxxxxxxxx]

On Thu, Oct 06, 2022 at 08:25:15AM +0000, David Laight wrote:
> From: Jim Mattson
> > Sent: 05 October 2022 23:29
> >
> > On Wed, Oct 5, 2022 at 3:03 PM Suraj Jitindar Singh <surajjs@xxxxxxxxxx> wrote:
> > >
> > > tl;dr: The existing mitigation for eIBRS PBRSB predictions uses an INT3 to
> > > ensure a call instruction retires before a following unbalanced RET. Replace
> > > this with a WRMSR serialising instruction which has a lower performance
> > > penalty.
> >
> > The INT3 is only on a speculative path and should not impact performance.
>
> Doesn't that depend on how quickly the cpu can abort the
> decode and execution of the INT3 instruction?
> INT3 is bound to generate a lot of uops and/or be microcoded.
>
> Old cpu couldn't abort fpu instructions.
> IIRC the Intel performance guide even suggested not interleaving
> code and data because the data might get speculatively executed
> and take a long time to abort.
>
> I actually wonder whether 'JMPS .' (eb fe) shouldn't be used
> instead of INT3 (cc) because it is fast to decode and execute.
> But I'm no expect here.

I have been told that INT3 is better in this case because 'JMP .' would
waste CPU resources.