Re: [PATCH 2/2] phy: qcom-qmp-ufs: Add SM7150 support

[Dmitry Baryshkov]

On Thu, 9 Mar 2023 at 20:51, Danila Tikhonov <danila@xxxxxxxxxxx> wrote:
>
> From: David Wronek <davidwronek@xxxxxxxxx>
>
> Add the tables and constants for init sequences for UFS QMP phy found in
> SM7150 SoC.
>
> Signed-off-by: David Wronek <davidwronek@xxxxxxxxx>
> Signed-off-by: Danila Tikhonov <danila@xxxxxxxxxxx>
> ---
>  drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 57 +++++++++++++++++++++++++
>  1 file changed, 57 insertions(+)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> index 994ddd5d4a81..b4f2d6c63beb 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> @@ -349,6 +349,36 @@ static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs[] = {
>         QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
>  };
>
> +static const struct qmp_phy_init_tbl sm7150_ufsphy_rx[] = {
> +       QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
> +       QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
> +       QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
> +       QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
> +       QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
> +       QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
> +       QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
> +       QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
> +       QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
> +       QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
> +       QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
> +       QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
> +       QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5b),

It is a pity to duplicate the whole table just for the single register
difference.

> +       QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
> +       QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
> +       QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
> +};
> +
> +static const struct qmp_phy_init_tbl sm7150_ufsphy_pcs[] = {
> +       QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2, 0x6f),
> +       QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
> +       QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
> +       QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL, 0x03),
> +       QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
> +       QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1, 0x0f),
> +       QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xFF),

s/0xFF/0xff/ , please

> +       QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
> +};)
> +
>  static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes[] = {
>         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
>         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
> @@ -911,6 +941,30 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
>         .no_pcs_sw_reset        = true,
>  };
>
> +static const struct qmp_phy_cfg sm7150_ufsphy_cfg = {

Please add offsets here. With that fixed:

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>

> +       .lanes                  = 1,
> +
> +       .tbls = {
> +               .serdes         = sdm845_ufsphy_serdes,
> +               .serdes_num     = ARRAY_SIZE(sdm845_ufsphy_serdes),
> +               .tx             = sdm845_ufsphy_tx,
> +               .tx_num         = ARRAY_SIZE(sdm845_ufsphy_tx),
> +               .rx             = sm7150_ufsphy_rx,
> +               .rx_num         = ARRAY_SIZE(sm7150_ufsphy_rx),
> +               .pcs            = sm7150_ufsphy_pcs,
> +               .pcs_num        = ARRAY_SIZE(sm7150_ufsphy_pcs),
> +       },
> +       .tbls_hs_b = {
> +               .serdes         = sdm845_ufsphy_hs_b_serdes,
> +               .serdes_num     = ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes),
> +       },
> +       .clk_list               = sdm845_ufs_phy_clk_l,
> +       .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
> +       .vreg_list              = qmp_phy_vreg_l,
> +       .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
> +       .regs                   = ufsphy_v3_regs_layout,

sdm845 has .no_pcs_sw_reset set to true. Do we need to set it for this PHY?

> +};
> +
>  static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
>         .lanes                  = 2,
>
> @@ -1560,6 +1614,9 @@ static const struct of_device_id qmp_ufs_of_match_table[] = {
>         }, {
>                 .compatible = "qcom,sm6350-qmp-ufs-phy",
>                 .data = &sdm845_ufsphy_cfg,
> +       }, {
> +               .compatible = "qcom,sm7150-qmp-ufs-phy",
> +               .data = &sm7150_ufsphy_cfg,
>         }, {
>                 .compatible = "qcom,sm8150-qmp-ufs-phy",
>                 .data = &sm8150_ufsphy_cfg,
> --
> 2.39.2
>


-- 
With best wishes
Dmitry