Re: [PATCH] LoongArch: Fixup cmpxchg sematic for memory barrier

[Xi Ruoyao]

On Tue, 2023-08-01 at 19:23 +0800, Xi Ruoyao wrote:
> On Tue, 2023-08-01 at 18:49 +0800, Guo Ren wrote:
> > > On Tue, Aug 1, 2023 at 5:05 PM Guo Ren <guoren@xxxxxxxxxx> wrote:
> > > > 
> > > > > The CoRR problem would cause wider problems than this.For this case,
> > > > > do you mean your LL -> LL would be reordered?
> > > > > 
> > > > > CPU 0
> > > > >            CPU1
> > > > > LL(2) (set ex-monitor)
> > > > > 
> > > > >                  store (break the ex-monitor)
> > > > > LL(1) (reordered instruction set ex-monitor
> > > > > SC(3) (successes ?)
> > > > Sorry for the mail client reformat, I mean:
> > > > 
> > > > CPU0  LL(2) (set ex-monitor)
> > > > CPU1  STORE (break the ex-monitor)
> > > > CPU0  LL(1) (reordered instruction set ex-monitor
> > > > CPU0  SC(3) (success?)
> > > 
> > > No. LL and LL won't reorder because LL implies a memory barrier(though
> > > not acquire semantics).
> > That means we could remove __WEAK_LLSC_MB totally, right?
> 
> As I've said, to implement CAS on LA464 this barrier is *really* needed.
> I initially didn't believe it then I spent one night (from 11 PM to 04
> AM) debugging GCC libgomp test failures.
> 
> On LA664 (3A6000) things may change though.

And I consider this a hardware bug, so it's out of the general concept
of general memory orders.  We are basically just applying a workaround
provided by uarch designers.

-- 
Xi Ruoyao <xry111@xxxxxxxxxxx>
School of Aerospace Science and Technology, Xidian University