Re: [PATCH] x86_64: Show CR4.PSE on auxiliaries like on BSP

[Peter Zijlstra]

On Mon, Aug 14, 2023 at 07:53:18PM -0700, Hugh Dickins wrote:
> Set CR4.PSE in secondary_startup_64: the Intel SDM is clear that it does
> not matter whether it's 0 or 1 when 4-level-pts are enabled, but it's
> distracting to find CR4 different on BSP and auxiliaries - on x86_64,
> BSP alone got to add the PSE bit, in probe_page_size_mask().

Specifically I think the point is that PSE bit is completely without
meaning in long mode IIRC.

But yes, having the same CR4 bits set across BSP and APs is definitely
sane.

Acked-by: Peter Zijlstra (Intel) <peterz@xxxxxxxxxxxxx>

> Signed-off-by: Hugh Dickins <hughd@xxxxxxxxxx>
> ---
>  arch/x86/kernel/head_64.S | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S
> index c5b9289837dc..72e36739c407 100644
> --- a/arch/x86/kernel/head_64.S
> +++ b/arch/x86/kernel/head_64.S
> @@ -181,8 +181,8 @@ SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_GLOBAL)
>  	movl	$0, %ecx
>  #endif
>  
> -	/* Enable PAE mode, PGE and LA57 */
> -	orl	$(X86_CR4_PAE | X86_CR4_PGE), %ecx
> +	/* Enable PAE mode, PSE, PGE and LA57 */
> +	orl	$(X86_CR4_PAE | X86_CR4_PSE | X86_CR4_PGE), %ecx
>  #ifdef CONFIG_X86_5LEVEL
>  	testl	$1, __pgtable_l5_enabled(%rip)
>  	jz	1f
> -- 
> 2.35.3
>