Thanks for sorting this out.
It seems like we have a few combinations of these interrupts and we
should probably try to define the order for these once and for all and
update the current devicetrees to match (even if it means adding new
interrupts in the middle).
Instead of adding separate compatibles for the controllers without SS
support, I suggest keeping that interrupt last as an optional one.
But IIUC we essentially have something like:
qusb2-:
- const: qusb2_phy
- const: pwr_event
- const: ss_phy_irq (optional)
qusb2:
- const: hs_phy_irq
- const: qusb2_phy
- const: pwr_event
- const: ss_phy_irq (optional)
qusb2+:
- const: hs_phy_irq
- const: qusb2_phy
- const: dp_hs_phy_irq
- const: dm_hs_phy_irq
- const: pwr_event
- const: ss_phy_irq (optional)
femto-:Yes. From whatever targets I was able to find, only one of them didn't have the power_event irq. Rest all of them had. I will recheck that particular one again.
- const: dp_hs_phy_irq
- const: dm_hs_phy_irq
- const: pwr_event
- const: ss_phy_irq (optional)
femto:
- const: hs_phy_irq
- const: dp_hs_phy_irq
- const: dm_hs_phy_irq
- const: pwr_event
- const: ss_phy_irq (optional)
Does this look like it would cover all of our currents SoCs?
Do all of them have the pwr_event interrupt?
Note that DP comes before DM above as that seems like the natural order
of these (plus before minus).
Now if the HS interrupt is truly unusable, I guess we can consider
dropping it throughout and the above becomes just three permutations
instead, which can even be expressed along the lines of:
- anyOf:
- items:
- const: qusb2_phy
- items:
- const: dp_hs_phy_irq
- const: dm_hs_phy_irq
- const: pwr_event
- const: ss_phy_irq (optional)