Re: [PATCH] scsi: ufs: qcom: Add missing interconnect bandwidth values for Gear 5

[Amit Pundir]

On Mon, 1 Apr 2024 at 20:39, Manivannan Sadhasivam
<manivannan.sadhasivam@xxxxxxxxxx> wrote:
>
> These entries are necessary to scale the interconnect bandwidth while
> operating in Gear 5.

This fixes the UFS breakage we see on SM8550-HDK.

Tested-by: Amit Pundir <amit.pundir@xxxxxxxxxx>

Regards,
Amit Pundir

>
> Cc: Amit Pundir <amit.pundir@xxxxxxxxxx>
> Fixes: 03ce80a1bb86 ("scsi: ufs: qcom: Add support for scaling interconnects")
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
> ---
>  drivers/ufs/host/ufs-qcom.c | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
> index 8d68bd21ae73..696540ca835e 100644
> --- a/drivers/ufs/host/ufs-qcom.c
> +++ b/drivers/ufs/host/ufs-qcom.c
> @@ -47,7 +47,7 @@ enum {
>         TSTBUS_MAX,
>  };
>
> -#define QCOM_UFS_MAX_GEAR 4
> +#define QCOM_UFS_MAX_GEAR 5
>  #define QCOM_UFS_MAX_LANE 2
>
>  enum {
> @@ -67,26 +67,32 @@ static const struct __ufs_qcom_bw_table {
>         [MODE_PWM][UFS_PWM_G2][UFS_LANE_1] = { 1844,            1000 },
>         [MODE_PWM][UFS_PWM_G3][UFS_LANE_1] = { 3688,            1000 },
>         [MODE_PWM][UFS_PWM_G4][UFS_LANE_1] = { 7376,            1000 },
> +       [MODE_PWM][UFS_PWM_G5][UFS_LANE_1] = { 14752,           1000 },
>         [MODE_PWM][UFS_PWM_G1][UFS_LANE_2] = { 1844,            1000 },
>         [MODE_PWM][UFS_PWM_G2][UFS_LANE_2] = { 3688,            1000 },
>         [MODE_PWM][UFS_PWM_G3][UFS_LANE_2] = { 7376,            1000 },
>         [MODE_PWM][UFS_PWM_G4][UFS_LANE_2] = { 14752,           1000 },
> +       [MODE_PWM][UFS_PWM_G5][UFS_LANE_2] = { 29504,           1000 },
>         [MODE_HS_RA][UFS_HS_G1][UFS_LANE_1] = { 127796,         1000 },
>         [MODE_HS_RA][UFS_HS_G2][UFS_LANE_1] = { 255591,         1000 },
>         [MODE_HS_RA][UFS_HS_G3][UFS_LANE_1] = { 1492582,        102400 },
>         [MODE_HS_RA][UFS_HS_G4][UFS_LANE_1] = { 2915200,        204800 },
> +       [MODE_HS_RA][UFS_HS_G5][UFS_LANE_1] = { 5836800,        409600 },
>         [MODE_HS_RA][UFS_HS_G1][UFS_LANE_2] = { 255591,         1000 },
>         [MODE_HS_RA][UFS_HS_G2][UFS_LANE_2] = { 511181,         1000 },
>         [MODE_HS_RA][UFS_HS_G3][UFS_LANE_2] = { 1492582,        204800 },
>         [MODE_HS_RA][UFS_HS_G4][UFS_LANE_2] = { 2915200,        409600 },
> +       [MODE_HS_RA][UFS_HS_G5][UFS_LANE_2] = { 5836800,        819200 },
>         [MODE_HS_RB][UFS_HS_G1][UFS_LANE_1] = { 149422,         1000 },
>         [MODE_HS_RB][UFS_HS_G2][UFS_LANE_1] = { 298189,         1000 },
>         [MODE_HS_RB][UFS_HS_G3][UFS_LANE_1] = { 1492582,        102400 },
>         [MODE_HS_RB][UFS_HS_G4][UFS_LANE_1] = { 2915200,        204800 },
> +       [MODE_HS_RB][UFS_HS_G5][UFS_LANE_1] = { 5836800,        409600 },
>         [MODE_HS_RB][UFS_HS_G1][UFS_LANE_2] = { 298189,         1000 },
>         [MODE_HS_RB][UFS_HS_G2][UFS_LANE_2] = { 596378,         1000 },
>         [MODE_HS_RB][UFS_HS_G3][UFS_LANE_2] = { 1492582,        204800 },
>         [MODE_HS_RB][UFS_HS_G4][UFS_LANE_2] = { 2915200,        409600 },
> +       [MODE_HS_RB][UFS_HS_G5][UFS_LANE_2] = { 5836800,        819200 },
>         [MODE_MAX][0][0]                    = { 7643136,        307200 },
>  };
>
>
> ---
> base-commit: 4cece764965020c22cff7665b18a012006359095
> change-id: 20240401-ufs-icc-fix-123c7ca1be45
>
> Best regards,
> --
> Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
>