Re: [PATCH] clk: sophgo: Use div64 for fpll rate calculation

[Chen Wang]

Just a minor suggestion to add soc name in email title to differ against 
other sophgo products. This can be handled in later patch if any.

Reviewed-by: Chen Wang <unicorn_wang@xxxxxxxxxxx>

On 2024/4/13 8:53, Inochi Amaoto wrote:
> The CV1800 SoC needs to use 64-bit division for fpll rate
> calculation, which will cause problem on 32-bit system.
> Use div64 series function to avoid this problem.
>
> Fixes: 80fd61ec4612 ("clk: sophgo: Add clock support for CV1800 SoC")
> Signed-off-by: Inochi Amaoto <inochiama@xxxxxxxxxxx>
> Reported-by: kernel test robot <lkp@xxxxxxxxx>
> Closes: https://lore.kernel.org/oe-kbuild-all/202404122344.d5pb2N1I-lkp@xxxxxxxxx/
> ---
>   drivers/clk/sophgo/clk-cv18xx-pll.c | 9 +++++----
>   1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/clk/sophgo/clk-cv18xx-pll.c b/drivers/clk/sophgo/clk-cv18xx-pll.c
> index c546dad1791c..65aba3b95cf7 100644
> --- a/drivers/clk/sophgo/clk-cv18xx-pll.c
> +++ b/drivers/clk/sophgo/clk-cv18xx-pll.c
> @@ -6,6 +6,7 @@
>   #include <linux/clk-provider.h>
>   #include <linux/io.h>
>   #include <linux/limits.h>
> +#include <linux/math64.h>
>   #include <linux/spinlock.h>
>
>   #include "clk-cv18xx-pll.h"
> @@ -202,18 +203,18 @@ static unsigned long fpll_calc_rate(unsigned long parent_rate,
>   {
>   	u64 dividend = parent_rate * div_sel;
>   	u64 factor = ssc_syn_set * pre_div_sel * post_div_sel;
> +	u64 remainder;
>   	unsigned long rate;
>
>   	dividend <<= PLL_SYN_FACTOR_DOT_POS - 1;
> -	rate = dividend / factor;
> -	dividend %= factor;
> +	rate = div64_u64_rem(dividend, factor, &remainder);
>
>   	if (is_full_parent) {
> -		dividend <<= 1;
> +		remainder <<= 1;
>   		rate <<= 1;
>   	}
>
> -	rate += DIV64_U64_ROUND_CLOSEST(dividend, factor);
> +	rate += DIV64_U64_ROUND_CLOSEST(remainder, factor);
>
>   	return rate;
>   }
> --
> 2.44.0