Re: [PATCH 2/4] dt-bindings: clock: Add R9A09G057 CPG Clock and Reset Definitions

[Geert Uytterhoeven]

Hi Prabhakar,

On Fri, May 24, 2024 at 10:29 AM Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> Define RZ/V2H(P) (R9A09G057) Clock Pulse Generator module clock outputs
> (CPG_CLK_ON* registers), and reset definitions (CPG_RST_* registers)
> in Section 4.4.2 and 4.4.3 ("List of Clock/Reset Signals") of the RZ/V2H(P)
> Hardware User's Manual (Rev.1.01, Feb. 2024).
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>

Thanks for your patch!

> --- /dev/null
> +++ b/include/dt-bindings/clock/r9a09g057-cpg.h
> @@ -0,0 +1,644 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> + *
> + * Copyright (C) 2024 Renesas Electronics Corp.
> + */
> +#ifndef __DT_BINDINGS_CLOCK_R9A09G057_CPG_H__
> +#define __DT_BINDINGS_CLOCK_R9A09G057_CPG_H__
> +
> +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> +
> +/* Clock list */

No distinction between Core and Module clocks?

> +#define R9A09G057_SYS_0_PCLK                           0
> +#define R9A09G057_DMAC_0_ACLK                          1
> +#define R9A09G057_DMAC_1_ACLK                          2
> +#define R9A09G057_DMAC_2_ACLK                          3

[...]

> +/* Resets list */

[...]

No power domain specifiers, as mentioned in PATCH 1/4?

> +
> +#endif /* __DT_BINDINGS_CLOCK_R9A09G057_CPG_H__ */

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68korg

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds