[PATCH] arm64: dts: qcom: sm8650-hdk: allow more IOMMU SID for the first QUP instance

[Neil Armstrong]

When triggering I2S SE DMA transfers on the 6th Serial Element, we get
some timeouts and finally a fatal SMMU crash because the I2C6 lines
are shared with the secure firmware in order to handle the SMB1396
charger from the secure side.

In order to make thing work flawlessly we need to allow more SIDs
while running our SE DMA transfers, thus add the 0x3 mark to allow
the 0xa0 SID to trigger while we trigger an 0xa3 SID from Linux.

This crash doesn't happen on the QRD platform since the SE6 is
configured differently, with FIFO mode disabled, thus GPI DMA
is used and we cannot exercise SE DMA on this interface.

The crash only happens when large tranfers occurs (>32 bytes) since
the driver is designed to use the SE DMA in this case, and there's
no way to mark the SE DMA as disabled or mark the GPI DMA as
preferred since the FIFO/SE DMA will be used is FIFO is not disabled.

Signed-off-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx>
---
 arch/arm64/boot/dts/qcom/sm8650-hdk.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts
index 182864a3b6bd..5887d265a077 100644
--- a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts
@@ -991,6 +991,8 @@ &qup_i2c3_data_clk {
 };
 
 &qupv3_id_0 {
+	iommus = <&apps_smmu 0xa3 0x3>;
+
 	status = "okay";
 };
 

---
base-commit: 234cb065ad82915ff8d06ce01e01c3e640b674d2
change-id: 20240605-topic-sm8650-upstream-hdk-iommu-fix-542619065c45

Best regards,
-- 
Neil Armstrong <neil.armstrong@xxxxxxxxxx>