Re: [PATCH] arm64: dts: qcom: sm8650-hdk: allow more IOMMU SID for the first QUP instance

[Konrad Dybcio]

On 5.06.2024 1:43 PM, Neil Armstrong wrote:
> When triggering I2S SE DMA transfers on the 6th Serial Element, we get
> some timeouts and finally a fatal SMMU crash because the I2C6 lines
> are shared with the secure firmware in order to handle the SMB1396
> charger from the secure side.
> 
> In order to make thing work flawlessly we need to allow more SIDs
> while running our SE DMA transfers, thus add the 0x3 mark to allow
> the 0xa0 SID to trigger while we trigger an 0xa3 SID from Linux.
> 
> This crash doesn't happen on the QRD platform since the SE6 is
> configured differently, with FIFO mode disabled, thus GPI DMA
> is used and we cannot exercise SE DMA on this interface.
> 
> The crash only happens when large tranfers occurs (>32 bytes) since
> the driver is designed to use the SE DMA in this case, and there's
> no way to mark the SE DMA as disabled or mark the GPI DMA as
> preferred since the FIFO/SE DMA will be used is FIFO is not disabled.
> 
> Signed-off-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx>
> ---

there's only 24 I2C masters on this soc, surely the board designer couldn't
have chosen another one for the charger..

Fixes: 01061441029e ("arm64: dts: qcom: sm8650: add support for the SM8650-HDK board")
Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>

Konrad