Re: [PATCH 2/7] arm64: dts: imx8qm: add mipi subsystem

From: Alexander Stein
Date: Fri Jun 07 2024 - 02:42:02 EST

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Hi,

thanks for the patch.
What are your plans regarding imx8xqp? This memory region
has dual use on imx8qxp mipi/lvds0. I would prefer
imx8-ss-mipi.dtsi with common parts and a imx8qm-ss-mipi.dtsi
adding/modifying imx8qm specific things. I'll send my current WIP
as a response to this.

Best regards,
Alexander

Am Donnerstag, 6. Juni 2024, 20:46:56 CEST schrieb Frank Li:
> Add irqstear, pwm and i2c in mipi subsystem.
>
> Signed-off-by: Frank Li <Frank.Li@xxxxxxx>
> ---
> arch/arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi | 286 ++++++++++++++++++++++
> arch/arm64/boot/dts/freescale/imx8qm.dtsi | 1 +
> 2 files changed, 287 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi
> new file mode 100644
> index 0000000000000..bd18468923e52
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi
> @@ -0,0 +1,286 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +
> +/*
> + * Copyright 2024 NXP
> + */
> +
> +/ {
> + dsi_ipg_clk: clock-dsi-ipg {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <120000000>;
> + clock-output-names = "dsi_ipg_clk";
> + };
> +
> + mipi_pll_div2_clk: clock-mipi-div2-pll {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <432000000>;
> + clock-output-names = "mipi_pll_div2_clk";
> + };
> +
> + mipi0_subsys: bus@56220000 {
> + compatible = "simple-bus";
> + interrupt-parent = <&irqsteer_mipi0>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x56220000 0x0 0x56220000 0x10000>;
> +
> + irqsteer_mipi0: interrupt-controller@56220000 {
> + compatible = "fsl,imx-irqsteer";

compatible = "fsl,imx8qxp-irqsteer", "fsl,imx-irqsteer" or even
compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer". Please refer to [1].

[1] https://lore.kernel.org/all/20240528071141.92003-1-alexander.stein@xxxxxxxxxxxxxxx/

> + reg = <0x56220000 0x1000>;
> + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + interrupt-parent = <&gic>;
> + #interrupt-cells = <1>;
> + clocks = <&mipi0_lis_lpcg IMX_LPCG_CLK_0>;
> + clock-names = "ipg";
> + power-domains = <&pd IMX_SC_R_MIPI_0>;
> + fsl,channel = <0>;
> + fsl,num-irqs = <32>;
> + };
> +
> + mipi0_lis_lpcg: clock-controller@56223000 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x56223000 0x4>;
> + #clock-cells = <1>;
> + clocks = <&dsi_ipg_clk>;
> + clock-indices = <IMX_LPCG_CLK_0>;
> + clock-output-names = "mipi0_lis_lpcg_ipg_clk";
> + power-domains = <&pd IMX_SC_R_MIPI_0>;
> + };
> +
> + mipi0_pwm_lpcg: clock-controller@5622300c {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x5622300c 0x4>;
> + #clock-cells = <1>;
> + clocks = <&clk IMX_SC_R_MIPI_0_PWM_0 IMX_SC_PM_CLK_PER>,
> + <&dsi_ipg_clk>;
> + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> + clock-output-names = "mipi0_pwm_lpcg_clk",
> + "mipi0_pwm_lpcg_ipg_clk";
> + power-domains = <&pd IMX_SC_R_MIPI_0_PWM_0>;
> + };
> +
> + mipi0_i2c0_lpcg_ipg_clk: clock-controller@56223014 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x56223014 0x4>;
> + #clock-cells = <1>;
> + clocks = <&mipi0_i2c0_lpcg_ipg_s_clk IMX_LPCG_CLK_0>;
> + clock-indices = <IMX_LPCG_CLK_0>;
> + clock-output-names = "mipi0_i2c0_lpcg_ipg_clk";
> + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
> + };
> +
> + mipi0_i2c0_lpcg_ipg_s_clk: clock-controller@56223018 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x56223018 0x4>;
> + #clock-cells = <1>;
> + clocks = <&dsi_ipg_clk>;
> + clock-indices = <IMX_LPCG_CLK_0>;
> + clock-output-names = "mipi0_i2c0_lpcg_ipg_s_clk";
> + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
> + };
> +
> + mipi0_i2c0_lpcg_clk: clock-controller@5622301c {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x5622301c 0x4>;
> + #clock-cells = <1>;
> + clocks = <&clk IMX_SC_R_MIPI_0_I2C_0 IMX_SC_PM_CLK_MISC2>;
> + clock-indices = <IMX_LPCG_CLK_0>;
> + clock-output-names = "mipi0_i2c0_lpcg_clk";
> + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
> + };
> +
> + mipi0_i2c1_lpcg_ipg_clk: clock-controller@56223024 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x56223024 0x4>;
> + #clock-cells = <1>;
> + clocks = <&mipi0_i2c1_lpcg_ipg_s_clk IMX_LPCG_CLK_0>;
> + clock-indices = <IMX_LPCG_CLK_0>;
> + clock-output-names = "mipi0_i2c1_lpcg_ipg_clk";
> + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>;
> + };
> +
> + mipi0_i2c1_lpcg_clk: clock-controller@5622302c {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x5622302c 0x4>;
> + #clock-cells = <1>;
> + clocks = <&clk IMX_SC_R_MIPI_0_I2C_1 IMX_SC_PM_CLK_MISC2>;
> + clock-indices = <IMX_LPCG_CLK_0>;
> + clock-output-names = "mipi0_i2c1_lpcg_clk";
> + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>;
> + };
> +
> + mipi0_i2c1_lpcg_ipg_s_clk: clock-controller@56223028 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x56223028 0x4>;
> + #clock-cells = <1>;
> + clocks = <&dsi_ipg_clk>;
> + clock-indices = <IMX_LPCG_CLK_0>;
> + clock-output-names = "mipi0_i2c1_lpcg_ipg_s_clk";
> + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>;
> + };
> +
> + pwm_mipi0: pwm@56224000 {
> + compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
> + reg = <0x56224000 0x1000>;
> + clocks = <&mipi0_pwm_lpcg IMX_LPCG_CLK_4>,
> + <&mipi0_pwm_lpcg IMX_LPCG_CLK_0>;
> + clock-names = "ipg", "per";
> + assigned-clocks = <&clk IMX_SC_R_MIPI_0_PWM_0 IMX_SC_PM_CLK_PER>;
> + assigned-clock-rates = <24000000>;
> + #pwm-cells = <3>;
> + power-domains = <&pd IMX_SC_R_MIPI_0_PWM_0>;
> + status = "disabled";
> + };
> +
> + i2c0_mipi0: i2c@56226000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
> + reg = <0x56226000 0x1000>;
> + interrupts = <8>;
> + clocks = <&mipi0_i2c0_lpcg_clk IMX_LPCG_CLK_0>,
> + <&mipi0_i2c0_lpcg_ipg_clk IMX_LPCG_CLK_0>;
> + clock-names = "per", "ipg";
> + assigned-clocks = <&mipi0_i2c0_lpcg_clk IMX_LPCG_CLK_0>;
> + assigned-clock-rates = <24000000>;
> + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
> + status = "disabled";
> + };
> + };
> +
> + mipi1_subsys: bus@57220000 {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x57220000 0x0 0x57220000 0x10000>;
> +
> + irqsteer_mipi1: interrupt-controller@57220000 {
> + compatible = "fsl,imx-irqsteer";
> + reg = <0x57220000 0x1000>;
> + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + interrupt-parent = <&gic>;
> + #interrupt-cells = <1>;
> + clocks = <&mipi1_lis_lpcg IMX_LPCG_CLK_0>;
> + clock-names = "ipg";
> + power-domains = <&pd IMX_SC_R_MIPI_1>;
> + fsl,channel = <0>;
> + fsl,num-irqs = <32>;
> + };
> +
> + mipi1_lis_lpcg: clock-controller@57223000 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x57223000 0x4>;
> + #clock-cells = <1>;
> + clocks = <&dsi_ipg_clk>;
> + clock-indices = <IMX_LPCG_CLK_0>;
> + clock-output-names = "mipi1_lis_lpcg_ipg_clk";
> + power-domains = <&pd IMX_SC_R_MIPI_1>;
> + };
> +
> + mipi1_pwm_lpcg: clock-controller@5722300c {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x5722300c 0x4>;
> + #clock-cells = <1>;
> + clocks = <&clk IMX_SC_R_MIPI_1_PWM_0 IMX_SC_PM_CLK_PER>,
> + <&dsi_ipg_clk>;
> + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> + clock-output-names = "mipi1_pwm_lpcg_clk",
> + "mipi1_pwm_lpcg_ipg_clk";
> + power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
> + };
> +
> + mipi1_i2c0_lpcg_clk: clock-controller@5722301c {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x5722301c 0x4>;
> + #clock-cells = <1>;
> + clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_MISC2>;
> + clock-indices = <IMX_LPCG_CLK_0>;
> + clock-output-names = "mipi1_i2c0_lpcg_clk";
> + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
> + };
> +
> + mipi1_i2c0_lpcg_ipg_clk: clock-controller@57223014 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x57223014 0x4>;
> + #clock-cells = <1>;
> + clocks = <&mipi1_i2c0_lpcg_ipg_s_clk IMX_LPCG_CLK_0>;
> + clock-indices = <IMX_LPCG_CLK_0>;
> + clock-output-names = "mipi1_i2c0_lpcg_ipg_clk";
> + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
> + };
> +
> + mipi1_i2c0_lpcg_ipg_s_clk: clock-controller@57223018 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x57223018 0x4>;
> + #clock-cells = <1>;
> + clocks = <&dsi_ipg_clk>;
> + clock-indices = <IMX_LPCG_CLK_0>;
> + clock-output-names = "mipi1_i2c0_lpcg_ipg_s_clk";
> + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
> + };
> +
> + mipi1_i2c1_lpcg_ipg_clk: clock-controller@57223024 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x57223024 0x4>;
> + #clock-cells = <1>;
> + clocks = <&mipi1_i2c1_lpcg_ipg_s_clk IMX_LPCG_CLK_0>;
> + clock-indices = <IMX_LPCG_CLK_0>;
> + clock-output-names = "mipi1_i2c1_lpcg_ipg_clk";
> + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>;
> + };
> +
> + mipi1_i2c1_lpcg_ipg_s_clk: clock-controller@57223028 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x57223028 0x4>;
> + #clock-cells = <1>;
> + clocks = <&dsi_ipg_clk>;
> + clock-indices = <IMX_LPCG_CLK_0>;
> + clock-output-names = "mipi1_i2c1_lpcg_ipg_s_clk";
> + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>;
> + };
> +
> + mipi1_i2c1_lpcg_clk: clock-controller@5722302c {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x5722302c 0x4>;
> + #clock-cells = <1>;
> + clocks = <&clk IMX_SC_R_MIPI_1_I2C_1 IMX_SC_PM_CLK_MISC2>;
> + clock-indices = <IMX_LPCG_CLK_0>;
> + clock-output-names = "mipi1_i2c1_lpcg_clk";
> + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>;
> + };
> +
> + pwm_mipi1: pwm@57224000 {
> + compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
> + reg = <0x57224000 0x1000>;
> + clocks = <&mipi1_pwm_lpcg IMX_LPCG_CLK_4>,
> + <&mipi1_pwm_lpcg IMX_LPCG_CLK_0>;
> + clock-names = "ipg", "per";
> + assigned-clocks = <&clk IMX_SC_R_MIPI_1_PWM_0 IMX_SC_PM_CLK_PER>;
> + assigned-clock-rates = <24000000>;
> + #pwm-cells = <3>;
> + power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
> + status = "disabled";
> + };
> +
> + i2c0_mipi1: i2c@57226000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
> + reg = <0x57226000 0x1000>;
> + interrupts = <8>;
> + interrupt-parent = <&irqsteer_mipi1>;
> + clocks = <&mipi1_i2c0_lpcg_clk IMX_LPCG_CLK_0>,
> + <&mipi1_i2c0_lpcg_ipg_clk IMX_LPCG_CLK_0>;
> + clock-names = "per", "ipg";
> + assigned-clocks = <&mipi1_i2c0_lpcg_clk IMX_LPCG_CLK_0>;
> + assigned-clock-rates = <24000000>;
> + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
> + status = "disabled";
> + };
> + };
> +};
> +
> diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
> index 9f29fe4589668..846b95be22bbe 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
> @@ -577,3 +577,4 @@ clk_spdif1_rx: clock-spdif1-rx {
> #include "imx8qm-ss-lsio.dtsi"
> #include "imx8qm-ss-audio.dtsi"
> #include "imx8qm-ss-lvds.dtsi"
> +#include "imx8qm-ss-mipi.dtsi"
>
>

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Next message: Krzysztof Kozlowski: "Re: [PATCH] i2c: muxes: pca954x: Allow sharing reset GPIO"
Previous message: Krzysztof Kozlowski: "Re: [PATCH v9 1/2] dt-bindings: net: wireless: qcom,ath11k: describe the ath11k on QCA6390"
In reply to: Peng Fan: "RE: [PATCH 2/7] arm64: dts: imx8qm: add mipi subsystem"
Next in thread: Alexander Stein: "[PATCH 1/1] [WIP] Initial DC0/LVDS0 subsystem files"
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]