Re: [PATCH v3 1/5] iommu/amd: Disable AMD IOMMU if CMPXCHG16B feature is not supported

From: Suthikulpanit, Suravee
Date: Mon Sep 16 2024 - 12:12:08 EST




On 9/6/2024 11:38 PM, Jason Gunthorpe wrote:
On Fri, Sep 06, 2024 at 12:13:04PM +0000, Suravee Suthikulpanit wrote:
According to the AMD IOMMU spec, the IOMMU reads the entire DTE either
in two 128-bit transactions or a single 256-bit transaction.

.. if two 128-bit transaction on the read side is possible then you
need flushing! :(

For instance this:

IOMMU CPU
Read [0]
Write [0]
Write [1]
Read [1]

Will result in the iommu seeing torn incorrect data - the Guest paging
mode may not match the page table pointer, or the VIOMMU data may
become mismatched to the host translation.

Avoiding flushing is only possible if the full 256 bits are read
atomically.

I have verified with the hardware designer, and they have now confirmed that the IOMMU hardware has always been implemented with 256-bit read. The next revision of the IOMMU spec will be updated to correctly describe this part. Therefore, I will update the commit message and implement the code accordingly.

It is recommended to update DTE using 128-bit operation followed by
an INVALIDATE_DEVTAB_ENTYRY command when the IV=1b or V=1b.

This advice only works when going from non-valid to valid.

Actually, if we change the DTE when IV=1 or V=1, we would need to invalidate as well.

Suggested-by: Jason Gunthorpe <jgg@xxxxxxxxxx>
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@xxxxxxx>
---
drivers/iommu/amd/init.c | 23 +++++++++--------------
1 file changed, 9 insertions(+), 14 deletions(-)

Reviewed-by: Jason Gunthorpe <jgg@xxxxxxxxxx>

Jason

Thanks,
Suravee