RE: [PATCH v3 3/3] x86/mce: Add CMCI storm switching support for Zhaoxin

From: Zhuo, Qiuxu
Date: Fri Sep 20 2024 - 05:17:31 EST


> From: Tony W Wang-oc <TonyWWang-oc@xxxxxxxxxxx>
> [...]
> Subject: [PATCH v3 3/3] x86/mce: Add CMCI storm switching support for
> [...]
> --- a/arch/x86/kernel/cpu/mce/zhaoxin.c
> +++ b/arch/x86/kernel/cpu/mce/zhaoxin.c
> @@ -63,3 +63,21 @@ void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c)
> {
> intel_clear_lmce();
> }
> +
> +void mce_zhaoxin_handle_storm(int bank, bool on) {
> + unsigned long flags;
> + u64 val;
> +
> + raw_spin_lock_irqsave(&cmci_discover_lock, flags);
> + rdmsrl(MSR_IA32_MCx_CTL2(bank), val);
> + if (on) {
> + val &= ~(MCI_CTL2_CMCI_EN |
> MCI_CTL2_CMCI_THRESHOLD_MASK);
> + val |= CMCI_STORM_THRESHOLD;
> + } else {
> + val &= ~MCI_CTL2_CMCI_THRESHOLD_MASK;
> + val |= (MCI_CTL2_CMCI_EN | cmci_threshold[bank]);
> + }
> + wrmsrl(MSR_IA32_MCx_CTL2(bank), val);
> + raw_spin_unlock_irqrestore(&cmci_discover_lock, flags); }

Are there any reasons or comments why it needs to disable/enable the CMCI interrupt
here during a CMCI storm on/off? If not, then reuse mce_intel_handle_storm() to avoid
duplicating the code.

-Qiuxu