Re: [PATCH v3 3/3] x86/mce: Add CMCI storm switching support for Zhaoxin
From: Yazen Ghannam
Date: Fri Sep 20 2024 - 09:23:35 EST
On Fri, Sep 20, 2024 at 06:42:15PM +0800, Tony W Wang-oc wrote:
>
>
> On 2024/9/19 22:06, Yazen Ghannam wrote:
> >
> > > +void mce_zhaoxin_handle_storm(int bank, bool on)
> > > +{
> > > + unsigned long flags;
> > > + u64 val;
> > > +
> > > + raw_spin_lock_irqsave(&cmci_discover_lock, flags);
> > > + rdmsrl(MSR_IA32_MCx_CTL2(bank), val);
> > > + if (on) {
> > > + val &= ~(MCI_CTL2_CMCI_EN | MCI_CTL2_CMCI_THRESHOLD_MASK);
> > > + val |= CMCI_STORM_THRESHOLD;
> > > + } else {
> > > + val &= ~MCI_CTL2_CMCI_THRESHOLD_MASK;
> > > + val |= (MCI_CTL2_CMCI_EN | cmci_threshold[bank]);
> > > + }
> > > + wrmsrl(MSR_IA32_MCx_CTL2(bank), val);
> > > + raw_spin_unlock_irqrestore(&cmci_discover_lock, flags);
> > > +}
> >
> > Why does this need to be different than mce_intel_handle_storm()?
> >
>
> The reason is actually mentioned in the cover letter: "because Zhaoxin's UCR
> error is not reported through CMCI", and we want to disable CMCI interrupt
> when CMCI storm happened.
>
I see, so you want to disable the interrupt entirely rather than
reprogramming to a high value. Makes sense.
Thanks,
Yazen