Re: [v3 PATCH] iommu/arm-smmu-v3: Fix L1 stream table index calculation for 32-bit sid size

[Will Deacon]

On Tue, Oct 08, 2024 at 12:15:06PM -0300, Jason Gunthorpe wrote:
> On Tue, Oct 08, 2024 at 02:34:58PM +0100, Will Deacon wrote:
> 
> > This all looks a bit messy to me. The architecture guarantees that
> > 2-level stream tables are supported once we hit 7-bit SIDs and, although
> > the driver relaxes this to > 8-bit SIDs, we'll never run into overflow
> > problems in the linear table code above.
> 
> My original point was about the confidential compute position (sigh)
> that the untrusted hypverisor should not corrupt the driver.
> 
> So your statement is architecturally true, but we never check that
> IDR0_ST_LVL_2LVL is set if IDR1_SIDSIZE > 2**7, and so we can get into
> this situation where the hypervisor could trigger some kind of bad
> behavior.
> 
> > So I'm inclined to take Daniel's one-liner [1] which just chucks the
> > 'ULL' suffix into the 2-level case. Otherwise, we're in a weird
> 
> I think you should take it and let better be for the CC crowd.

Heh. I wish them luck! :p

Will