Re: [PATCH RESEND TO CC MAILLIST] i2c: designware: fix master holding SCL low when I2C_DYNAMIC_TAR_UPDATE not set

[Andy Shevchenko]

On Fri, Nov 01, 2024 at 04:12:43PM +0800, Liu Peibao wrote:
> When Tx FIFO empty and last command with no STOP bit set, the master
> holds SCL low. If I2C_DYNAMIC_TAR_UPDATE is not set, BIT(13) MST_ON_HOLD
> of IC_RAW_INTR_STAT is not Enabled, causing the __i2c_dw_disable()
> timeout. This is quiet similar as commit 2409205acd3c ("i2c: designware:
> fix __i2c_dw_disable() in case master is holding SCL low") mentioned.
> Check BIT(7) MST_HOLD_TX_FIFO_EMPTY in IC_STATUS also which is available
> when IC_STAT_FOR_CLK_STRETCH is set.

Who are those people? Why Angus Chen is not a committer of the change?
Please, consult with the Submitting Patches documentation to clarify on these
tags.

Also, sounds to me that Fixes tag is needed.

-- 
With Best Regards,
Andy Shevchenko