Re: [PATCH RESEND TO CC MAILLIST] i2c: designware: fix master holding SCL low when I2C_DYNAMIC_TAR_UPDATE not set

[Liu Peibao]

On 2024/11/1 16:44, Andy Shevchenko wrote:
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> On Fri, Nov 01, 2024 at 04:12:43PM +0800, Liu Peibao wrote:
>> When Tx FIFO empty and last command with no STOP bit set, the master
>> holds SCL low. If I2C_DYNAMIC_TAR_UPDATE is not set, BIT(13) MST_ON_HOLD
>> of IC_RAW_INTR_STAT is not Enabled, causing the __i2c_dw_disable()
>> timeout. This is quiet similar as commit 2409205acd3c ("i2c: designware:
>> fix __i2c_dw_disable() in case master is holding SCL low") mentioned.
>> Check BIT(7) MST_HOLD_TX_FIFO_EMPTY in IC_STATUS also which is available
>> when IC_STAT_FOR_CLK_STRETCH is set.
> 
> Who are those people? Why Angus Chen is not a committer of the change?
> Please, consult with the Submitting Patches documentation to clarify on these
> tags.
> 

We have discussed and analyzed this issue together. I developed this patch.
This patch was also reviewed by Angus Chen and Xiaowu Ding.

And in this case, should I replace the "SoBs" with "Reviewed-by"?

> Also, sounds to me that Fixes tag is needed.
> 

How about this tag:
Fixes: 2409205acd3c ("i2c: designware: fix __i2c_dw_disable() in case master is holding SCL low")

BR,
Peibao