Re: [PATCH RFC 4/7] x86/microcode/intel: Prepare for microcode staging

[Chang S. Bae]

On 11/4/2024 10:34 AM, Chang S. Bae wrote:
> On 11/4/2024 8:08 AM, Dave Hansen wrote:
> > On 11/4/24 03:16, Borislav Petkov wrote:
> > > On Tue, Oct 01, 2024 at 09:10:39AM -0700, Chang S. Bae wrote:
> > > > +static inline u64 staging_addr(u32 cpu)
> > > > +{
> > > > +    u32 lo, hi;
> > > > +
> > > > +    rdmsr_on_cpu(cpu, MSR_IA32_MCU_STAGING_MBOX_ADDR, &lo, &hi);
> > > > +    return lo | ((u64)hi << 32);
> > > > +}
> > > A single usage site. Move its code there and get rid of the function.
> >
> > Yeah, and it'll look a lot nicer if you use:
> >
> >     rdmsrl_on_cpu(cpu, MSR_IA32_MCU_STAGING_MBOX_ADDR, &addr);
> >
> > and don't have to do the high/lo munging.
>
> Oh, silly me missed this function. Thanks.

Okay, I took another look and found a similar case:

diff --git a/drivers/cpufreq/acpi-cpufreq.c b/drivers/cpufreq/acpi-cpufreq.c
index 0f04feb6cafa..b942cd11e179 100644
--- a/drivers/cpufreq/acpi-cpufreq.c
+++ b/drivers/cpufreq/acpi-cpufreq.c
@@ -73,20 +73,17 @@ static unsigned int acpi_pstate_strict;

 static bool boost_state(unsigned int cpu)
 {
-       u32 lo, hi;
        u64 msr;

        switch (boot_cpu_data.x86_vendor) {
        case X86_VENDOR_INTEL:
        case X86_VENDOR_CENTAUR:
        case X86_VENDOR_ZHAOXIN:
-               rdmsr_on_cpu(cpu, MSR_IA32_MISC_ENABLE, &lo, &hi);
-               msr = lo | ((u64)hi << 32);
+               rdmsrl_on_cpu(cpu, MSR_IA32_MISC_ENABLE, &msr);
                return !(msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE);
        case X86_VENDOR_HYGON:
        case X86_VENDOR_AMD:
-               rdmsr_on_cpu(cpu, MSR_K7_HWCR, &lo, &hi);
-               msr = lo | ((u64)hi << 32);
+               rdmsrl_on_cpu(cpu, MSR_K7_HWCR, &msr);
                return !(msr & MSR_K7_HWCR_CPB_DIS);
        }
        return false;

I'll be following up with a patch to clean this up as well.

Thanks,
Chang