Re: [PATCH RFC 4/7] x86/microcode/intel: Prepare for microcode staging
From: Dave Hansen
Date: Fri Nov 08 2024 - 17:51:57 EST
On 11/6/24 17:12, Thomas Gleixner wrote:
> This looks all overly complicated. The documentation says:
>
> "There is one set of mailbox registers and internal staging buffers per
> physical processor package. Therefore, the IA32_MCU_STAGING_MBOX_ADDR
> MSR is package-scoped and will provide a different physical address on
> each physical package."
>
> So why going through loops and hoops?
I'm to blame for that one.
It was the smallest amount of code I could think of at the time that
could work when all the CPUs in a package aren't consecutively numbered.
It also happens to work even if the topology parsing or firmware goes
wonky.