Re: [PATCH v3 05/10] clk: renesas: r8a779h0: Add display clocks

[Tomi Valkeinen]

Hi,

On 06/12/2024 15:43, Geert Uytterhoeven wrote:
> Hi Tomi,
>
> On Fri, Dec 6, 2024 at 10:33 AM Tomi Valkeinen
> <tomi.valkeinen@xxxxxxxxxxxxxxxx> wrote:
> > From: Tomi Valkeinen <tomi.valkeinen+renesas@xxxxxxxxxxxxxxxx>
> >
> > Add display related clocks for DU, DSI, FCPVD, and VSPD.
> >
> > Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@xxxxxxxxxxxxxxxx>
> > Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@xxxxxxxxxxxxxxxx>
> > Tested-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
> i.e. will queue in renesas-clk for v6.14.
>
> > --- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c
> > +++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c
> > @@ -179,6 +179,9 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] __initconst = {
> >          DEF_MOD("canfd0",       328,    R8A779H0_CLK_SASYNCPERD2),
> >          DEF_MOD("csi40",        331,    R8A779H0_CLK_CSI),
> >          DEF_MOD("csi41",        400,    R8A779H0_CLK_CSI),
> > +       DEF_MOD("dis0",         411,    R8A779H0_CLK_S0D3),
> > +       DEF_MOD("dsitxlink0",   415,    R8A779H0_CLK_DSIREF),
> > +       DEF_MOD("fcpvd0",       508,    R8A779H0_CLK_S0D3),
> >          DEF_MOD("hscif0",       514,    R8A779H0_CLK_SASYNCPERD1),
> >          DEF_MOD("hscif1",       515,    R8A779H0_CLK_SASYNCPERD1),
> >          DEF_MOD("hscif2",       516,    R8A779H0_CLK_SASYNCPERD1),
> > @@ -227,6 +230,7 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] __initconst = {
> >          DEF_MOD("vin15",        811,    R8A779H0_CLK_S0D4_VIO),
> >          DEF_MOD("vin16",        812,    R8A779H0_CLK_S0D4_VIO),
> >          DEF_MOD("vin17",        813,    R8A779H0_CLK_S0D4_VIO),
> > +       DEF_MOD("vspd0",        830,    R8A779H0_CLK_S0D1_VIO),
> >          DEF_MOD("wdt1:wdt0",    907,    R8A779H0_CLK_R),
> >          DEF_MOD("cmt0",         910,    R8A779H0_CLK_R),
> >          DEF_MOD("cmt1",         911,    R8A779H0_CLK_R),
>
> As mentioned by Laurent during his review on v1, all clock parents
> should probably be some form of R8A779H0_CLK_S0Dx_VIO.
> So I'm inclined to replace all of them by R8A779H0_CLK_VIOBUSD2 while
> applying, which would match R-Car V4H.

What do you mean with the above? First you say the clock parents should 
be some form of S0Dx_VIO, but then you say you'll use VIOBUSD2. Aren't 
those unrelated clocks, from different PLLs?

> Are you OK with that?

I'm fine with that. I can't really get much out of the docs wrt. 
clocking, and the clocks I used were from the BSP. Afaics, it looks 
similar to V4H, so it's probably best have the same clocks, as you suggest.

 Tomi