[PATCH v4 7/9] watchdog: rzv2h_wdt: Configure CPG_ERRORRST_SEL2 register

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>

Currently, the watchdog driver relies on TF-A/U-Boot to configure the
`CPG_ERRORRST_SEL2` register. This register must be set correctly to
ensure a reset request is issued upon watchdog timer (WDT) underflow.

Now that the driver has access to the `syscon` handle for CPG, configure
`CPG_ERRORRST_SEL2` directly instead of depending on firmware. This
improves robustness by ensuring the required configuration is applied
within the driver itself.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
---
v3->v4
- New patch
---
 drivers/watchdog/rzv2h_wdt.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/watchdog/rzv2h_wdt.c b/drivers/watchdog/rzv2h_wdt.c
index c9bdaa8f2e3a..04b8ee899353 100644
--- a/drivers/watchdog/rzv2h_wdt.c
+++ b/drivers/watchdog/rzv2h_wdt.c
@@ -43,6 +43,10 @@
 
 #define WDT_DEFAULT_TIMEOUT	60U
 
+#define CPG_ERRORRST_SEL2(x)	((x) - 0x3c)
+#define CPG_ERRRSTSELx(x)	BIT(x)
+#define CPG_ERRRSTSELx_WEN(x)	BIT((x) + 16)
+
 #define CPG_ERROR_RST2(x)	BIT(x)
 #define CPG_ERROR_RST2_WEN(x)	BIT((x) + 16)
 
@@ -246,6 +250,16 @@ static int rzv2h_wdt_probe(struct platform_device *pdev)
 				return ret;
 		}
 		bootstatus = val & CPG_ERROR_RST2(bit) ? WDIOF_CARDRESET : 0;
+
+		/*
+		 * configure CPG_ERRORRST_SEL2 register to issue a reset request
+		 * upon WDT underflow
+		 */
+		ret = regmap_write(syscon, CPG_ERRORRST_SEL2(offset),
+				   CPG_ERRRSTSELx(bit) |
+				   CPG_ERRRSTSELx_WEN(bit));
+		if (ret)
+			return ret;
 	}
 
 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
-- 
2.43.0