Re: [RESEND PATCH] clk: socfpga: clk-pll: Optimize local variables

[Dinh Nguyen]

On 2/19/25 04:42, Thorsten Blum wrote:
> Since readl() returns a u32, the local variables reg and bypass can also
> have the data type u32. Furthermore, divf and divq are derived from reg
> and can also be a u32.
>
> Since do_div() casts the divisor to u32 anyway, changing the data type
> of divq to u32 removes the following Coccinelle/coccicheck warning
> reported by do_div.cocci:
>
>    WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead
>
> Compile-tested only.
>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
> Signed-off-by: Thorsten Blum <thorsten.blum@xxxxxxxxx>
> ---
>   drivers/clk/socfpga/clk-pll.c | 4 ++--

Applied!

Thanks,
Dinh