Re: [Patch v2 10/24] perf/x86/intel: Process arch-PEBS records or record fragments

[Liang, Kan]

On 2025-02-26 4:35 a.m., Peter Zijlstra wrote:
> On Wed, Feb 26, 2025 at 01:20:37PM +0800, Mi, Dapeng wrote:
> 
>>> Also, should that workaround have been extended to also include
>>> GLOBAL_STATUS_PERF_METRICS_OVF in that mask, or was that defect fixed
>>> for every chip capable of metrics stuff?
>>
>> hmm,  per my understanding, GLOBAL_STATUS_PERF_METRICS_OVF handling should
>> only be skipped when fixed counter 3 or perf metrics are included in PEBS
>> counter group. In this case, the slots and topdown metrics have been
>> updated by PEBS handler. It should not be processed again.
>>
>> @Kan Liang, is it correct?
> 
> Right, so the thing is, *any* PEBS event pending will clear METRICS_OVF
> per:
> 
>                 status &= x86_pmu.intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI;
> 

Yes, we have to add it for both legacy PEBS and ARCH PEBS.

An alternative way may change the order of handling the overflow bit.

The commit daa864b8f8e3 ("perf/x86/pebs: Fix handling of PEBS buffer
overflows") has moved the "status &= ~cpuc->pebs_enabled;" out of PEBS
overflow code.

As long as the PEBS overflow is handled after PT, I don't think the
above is required anymore.

It should be similar to METRICS_OVF. But the PEBS counters snapshotting
should be specially handled, since the PEBS will handle the metrics
counter as well.

@@ -3211,7 +3211,8 @@ static int handle_pmi_common(struct pt_regs *regs,
u64 status)
 	/*
 	 * Intel Perf metrics
 	 */
-	if (__test_and_clear_bit(GLOBAL_STATUS_PERF_METRICS_OVF_BIT, (unsigned
long *)&status)) {
+	if (__test_and_clear_bit(GLOBAL_STATUS_PERF_METRICS_OVF_BIT, (unsigned
long *)&status) &&
+	
!is_pebs_counter_event_group(cpuc->events[INTEL_PMC_IDX_FIXED_SLOTS])) {
 		handled++;
 		static_call(intel_pmu_update_topdown_event)(NULL, NULL);
 	}


Thanks,
Kan