[PATCH] mtd: spi-nor: eon: fix lock and non-SFDP flags

[Jakub Czapiga]

Set appropriate FLASH lock feature flags for chips that support it.
Set top-bottom protection bit flag for chips that support it.
Add no-SFDP flags for chips with missing SFDP or without clear
SFDP description regarding 4K sectors, dual and quad read support.
Remove no-SFDP flags for chips which documentation states that this
information can be extracted from SFDP.

Modified chips:
- EN25Q32 (+lock)
- EN25Q64 (+lock)
- EN25Q32B (+lock, +tb, +4k, +dual, +quad)
- EN25Q64 (+lock, +tb, +dual, +quad)
- EN25F32 (+lock, +tb)
- EN25S64 (+lock, +tb, +4k, +dual, +quad)
- EN25QH16 (+lock, +tb, -4k, -dual)
- EN25QH32 (+lock, +tb)
- EN25QH64 (+lock, +tb, -4k, -dual)
- EN25QH128 (+lock, +tb)
- EN25QH256 (+lock, +tb)

Signed-off-by: Jakub Czapiga <czapiga@xxxxxxxxxx>
---
 drivers/mtd/spi-nor/eon.c | 19 +++++++++++++++----
 1 file changed, 15 insertions(+), 4 deletions(-)

diff --git a/drivers/mtd/spi-nor/eon.c b/drivers/mtd/spi-nor/eon.c
index c1ddf662f782..10ed06022a76 100644
--- a/drivers/mtd/spi-nor/eon.c
+++ b/drivers/mtd/spi-nor/eon.c
@@ -13,10 +13,12 @@ static const struct flash_info eon_nor_parts[] = {
 		.id = SNOR_ID(0x1c, 0x20, 0x16),
 		.name = "en25p32",
 		.size = SZ_4M,
+		.flags = SPI_NOR_HAS_LOCK,
 	}, {
 		.id = SNOR_ID(0x1c, 0x20, 0x17),
 		.name = "en25p64",
 		.size = SZ_8M,
+		.flags = SPI_NOR_HAS_LOCK,
 	}, {
 		.id = SNOR_ID(0x1c, 0x30, 0x14),
 		.name = "en25q80a",
@@ -26,42 +28,51 @@ static const struct flash_info eon_nor_parts[] = {
 		.id = SNOR_ID(0x1c, 0x30, 0x16),
 		.name = "en25q32b",
 		.size = SZ_4M,
+		.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+		.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
 	}, {
 		.id = SNOR_ID(0x1c, 0x30, 0x17),
 		.name = "en25q64",
 		.size = SZ_8M,
-		.no_sfdp_flags = SECT_4K,
+		.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+		.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
 	}, {
 		.id = SNOR_ID(0x1c, 0x31, 0x16),
 		.name = "en25f32",
 		.size = SZ_4M,
 		.no_sfdp_flags = SECT_4K,
+		.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
 	}, {
 		.name = "en25s64",
 		.id = SNOR_ID(0x1c, 0x38, 0x17),
 		.size = SZ_8M,
-		.no_sfdp_flags = SECT_4K,
+		.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+		.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
 	}, {
 		.id = SNOR_ID(0x1c, 0x70, 0x15),
 		.name = "en25qh16",
 		.size = SZ_2M,
-		.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ,
+		.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
 	}, {
 		.id = SNOR_ID(0x1c, 0x70, 0x16),
 		.name = "en25qh32",
 		.size = SZ_4M,
+		.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
 	}, {
 		.id = SNOR_ID(0x1c, 0x70, 0x17),
 		.name = "en25qh64",
 		.size = SZ_8M,
-		.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ,
+		.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
 	}, {
 		.id = SNOR_ID(0x1c, 0x70, 0x18),
 		.name = "en25qh128",
 		.size = SZ_16M,
+		.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
 	}, {
 		.id = SNOR_ID(0x1c, 0x70, 0x19),
 		.name = "en25qh256",
+		.size = SZ_32M,
+		.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
 	},
 };
 
-- 
2.49.0.rc1.451.g8f38331e32-goog