[PATCH] mtd: spi-nor: macronix: add MX77U25650F, MX77U25655F and MX77U51250F

[Jakub Czapiga]

MX77U25650F and MX77U25655F are 256Mbit chips with SFDP and block
protection support. MX77U51250F is 512Mbit chip with SFDP and block
protection support.
All chips also support top-bottom lock configuration, however this bit
is SR2(3) and is also OTP (defaults to top). Due to lack of API to
support TB in SR2(3) and due to it being OTP these chips will only
support top blocks protection.

Signed-off-by: Jakub Czapiga <czapiga@xxxxxxxxxx>
---
 drivers/mtd/spi-nor/macronix.c | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c
index 99936fd25d43..c65e7cdab5cf 100644
--- a/drivers/mtd/spi-nor/macronix.c
+++ b/drivers/mtd/spi-nor/macronix.c
@@ -193,7 +193,22 @@ static const struct flash_info macronix_nor_parts[] = {
 		.name = "mx25l3255e",
 		.size = SZ_4M,
 		.no_sfdp_flags = SECT_4K,
-	},
+	}, {
+		.id = SNOR_ID(0xc2, 0x75, 0x39),
+		.name = "mx77u25650f",
+		.size = SZ_32M,
+		.flags = SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP,
+	}, {
+		.id = SNOR_ID(0xc2, 0x76, 0x39),
+		.name = "mx77u25655f",
+		.size = SZ_32M,
+		.flags = SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP,
+	}, {
+		.id = SNOR_ID(0xc2, 0x75, 0x3a),
+		.name = "mx77u51250f",
+		.size = SZ_64M,
+		.flags = SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP,
+	}
 	/*
 	 * This spares us of adding new flash entries for flashes that can be
 	 * initialized solely based on the SFDP data, but still need the
-- 
2.49.0.rc1.451.g8f38331e32-goog