[PATCH v4 10/11] ARM: dts: microchip: sama7d65: Add RTT and GPBR Support for sama7d65 SoC

From: Ryan.Wanner
Date: Wed Mar 26 2025 - 11:41:41 EST


From: Ryan Wanner <Ryan.Wanner@xxxxxxxxxxxxx>

Add RTT support for SAMA7D65 SoC. The GPBR is added so the SoC is able
to store the RTT time data.

Signed-off-by: Ryan Wanner <Ryan.Wanner@xxxxxxxxxxxxx>
---
arch/arm/boot/dts/microchip/sama7d65.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi
index 7d71e7326e3a..59b43a633aef 100644
--- a/arch/arm/boot/dts/microchip/sama7d65.dtsi
+++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi
@@ -132,6 +132,13 @@ shdwc: poweroff@e001d200 {
status = "disabled";
};

+ rtt: rtc@e001d300 {
+ compatible = "microchip,sama7d65-rtt", "atmel,at91sam9260-rtt";
+ reg = <0xe001d300 0x30>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk32k 0>;
+ };
+
clk32k: clock-controller@e001d500 {
compatible = "microchip,sama7d65-sckc", "microchip,sam9x60-sckc";
reg = <0xe001d500 0x4>;
@@ -146,6 +153,11 @@ rtc: rtc@e001d800 {
clocks = <&clk32k 1>;
};

+ gpbr: syscon@e001d700 {
+ compatible = "microchip,sama7d65-gpbr", "syscon";
+ reg = <0xe001d700 0x48>;
+ };
+
chipid@e0020000 {
compatible = "microchip,sama7d65-chipid";
reg = <0xe0020000 0x8>;
--
2.43.0