Re: [PATCH v1 2/2] drm/panel-edp: Modify LQ116M1JW10 panel's bpc to 6

[Doug Anderson]

Hi,

On Wed, Oct 29, 2025 at 1:11 AM Ajye Huang
<ajye_huang@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx> wrote:
>
> The link training is failed when bpc value is 8.
> It sure seems like the panel simply doesn't like 8bpp,
> Changing the bpc to 6 allows link training to succeed.
>
> The 8bpc log shows that link training failed.
> 6bpc
> ----
> rate_mhz: 1620
> valid rates: 30
> bit_rate_khz: 2399760, dp_rate_mhz: 1500, ti_sn_bridge_calc_min_dp_rate_idx return: 1
>
> 8bpc
> ----
> rate_mhz: 2160
> valid rates: 30
> bit_rate_khz: 3199680, dp_rate_mhz: 2000, ti_sn_bridge_calc_min_dp_rate_idx return: 2
> Link training failed, link is off.
> Disable the PLL if we failed.

Though I always appreciate details about the debugging that was done,
I suspect that most people reading this won't really understand unless
you give them the context that you are using the ti-sn65dsi86 bridge
chip and that you are printing out values related to bridge training.

I would also note that, to me, the more important test was confirming
that even when you pick the same "rate_mhz" for 6bpc and 8bpc that
6bpc works and 8bpc doesn't work.


> Signed-off-by: Ajye Huang <ajye_huang@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx>
> ---
>  drivers/gpu/drm/panel/panel-edp.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Unless folks end up preferring EDID_QUIRK_FORCE_6BPC:

Reviewed-by: Douglas Anderson <dianders@xxxxxxxxxxxx>