[PATCH v1 2/2] drm/panel-edp: Modify LQ116M1JW10 panel's bpc to 6

[Ajye Huang]

The link training is failed when bpc value is 8.
It sure seems like the panel simply doesn't like 8bpp,
Changing the bpc to 6 allows link training to succeed.

The 8bpc log shows that link training failed.
6bpc
----
rate_mhz: 1620
valid rates: 30
bit_rate_khz: 2399760, dp_rate_mhz: 1500, ti_sn_bridge_calc_min_dp_rate_idx return: 1

8bpc
----
rate_mhz: 2160
valid rates: 30
bit_rate_khz: 3199680, dp_rate_mhz: 2000, ti_sn_bridge_calc_min_dp_rate_idx return: 2
Link training failed, link is off.
Disable the PLL if we failed.

Signed-off-by: Ajye Huang <ajye_huang@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx>
---
 drivers/gpu/drm/panel/panel-edp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/panel/panel-edp.c b/drivers/gpu/drm/panel/panel-edp.c
index da3e8f223ec3..13755168cd75 100644
--- a/drivers/gpu/drm/panel/panel-edp.c
+++ b/drivers/gpu/drm/panel/panel-edp.c
@@ -2094,7 +2094,7 @@ static const struct edp_panel_entry edp_panels[] = {
 	EDP_PANEL_ENTRY('S', 'H', 'P', 0x1511, &delay_200_500_e50, "LQ140M1JW48"),
 	EDP_PANEL_ENTRY('S', 'H', 'P', 0x1523, &delay_80_500_e50, "LQ140M1JW46"),
 	EDP_PANEL_ENTRY('S', 'H', 'P', 0x153a, &delay_200_500_e50, "LQ140T1JH01"),
-	EDP_PANEL_ENTRY('S', 'H', 'P', 0x154c, &delay_200_500_p2e100, "LQ116M1JW10"),
+	EDP_PANEL_ENTRY3('S', 'H', 'P', 0x154c, &delay_200_500_p2e100, "LQ116M1JW10", 6),
 	EDP_PANEL_ENTRY('S', 'H', 'P', 0x158f, &delay_200_500_p2e100, "LQ134Z1"),
 	EDP_PANEL_ENTRY('S', 'H', 'P', 0x1593, &delay_200_500_p2e100, "LQ134N1"),
 
-- 
2.25.1