Re: [PATCH v4 5/7] PCI: spacemit: introduce SpacemiT PCIe host driver

[Aurelien Jarno]

Hi Alex,

On 2025-10-30 17:02, Alex Elder wrote:
> +/* Disable ASPM L1 for now, until reported errors can be reproduced */

Thanks for adding this function.

> +static void k1_pcie_post_init(struct dw_pcie_rp *pp)
> +{
> +	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> +	u8 offset;
> +	u32 val;
> +
> +	offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> +
> +	dw_pcie_dbi_ro_wr_en(pci);
> +
> +	/* Turn off ASPM L1 for the link */
> +	val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);

Why not using dw_pcie_readl_dbi() instead?

> +	val &= ~PCI_EXP_LNKCAP_ASPM_L1;
> +	writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP);

And here dw_pcie_writel_dbi()?

> +
> +	dw_pcie_dbi_ro_wr_dis(pci);
> +}
> +
> +static void k1_pcie_deinit(struct dw_pcie_rp *pp)
> +{
> +	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> +	struct k1_pcie *k1 = to_k1_pcie(pci);
> +
> +	/* Assert fundamental reset (drive PERST# low) */
> +	regmap_set_bits(k1->pmu, k1->pmu_off + PCIE_CLK_RESET_CONTROL,
> +			PCIE_RC_PERST);
> +
> +	phy_exit(k1->phy);
> +
> +	k1_pcie_disable_resources(k1);
> +}
> +
> +static const struct dw_pcie_host_ops k1_pcie_host_ops = {
> +	.init		= k1_pcie_init,
> +	.post_init	= k1_pcie_post_init,

Unfortunately, while I can see the effect of the change with for 
instance lspci -vvv, this happens way too late in the device scan 
process, i.e. after pcie_aspm_override_default_link_state() and causes 
L1 to still be enabled.

I have tried to move it earlier, in k1_pcie_init() after writing the 
vendor and device IDs. This works as long as "nvme scan" is run in 
U-Boot. But if I don't run this command, it seems that the change is 
ignored or lost (i.e. I can still see L1 enabled with lspci -vvv).

Moving it at the end of k1_pcie_init() works fine, like moving it at the 
beginning of k1_pcie_start_link(). But my knowledge is too limited to 
know where is the correct place.

Regards
Aurelien

-- 
Aurelien Jarno                          GPG: 4096R/1DDD8C9B
aurelien@xxxxxxxxxxx                     http://aurel32.net