Re: [PATCH] EDAC/altera: Handle OCRAM ECC enable after warm reset

[Niravkumar L Rabara]

On 10/11/2025 2:57 am, Borislav Petkov wrote:
> On Mon, Nov 03, 2025 at 10:09:20PM +0800, niravkumarlaxmidas.rabara@xxxxxxxxxx wrote:
> > From: Niravkumar L Rabara <niravkumarlaxmidas.rabara@xxxxxxxxxx>
> >
> > The OCRAM ECC is always enabled either by the BootROM or by the Secure
> > Device Manager (SDM) during a power-on reset on SoCFPGA.
> >
> > However, during a warm reset, the OCRAM content is retained to preserve
> > data, while the control and status registers are reset to their default
> > values. As a result, ECC must be explicitly re-enabled after a warm reset.
> >
> > Signed-off-by: Niravkumar L Rabara <niravkumarlaxmidas.rabara@xxxxxxxxxx>
> > ---
> >   drivers/edac/altera_edac.c | 18 +++++++++++++++---
> >   1 file changed, 15 insertions(+), 3 deletions(-)
>
> Does this need to go stable?
>
> Fixes: tag?

Yes, I missed it.
Will send v2 patch with the Fixes and CC tags.

Thanks,
Nirav