Re: [PATCH 1/2] pmdomain: imx8m-blk-ctrl: Remove separate rst and clk mask for 8mq vpu

[Ming Qian(OSS)]

Hi Nicolas,

On 11/22/2025 2:07 AM, Nicolas Dufresne wrote:
> Hi Ming,
>
> thanks a lot for working on this.
>
> Le vendredi 21 novembre 2025 à 16:19 +0800, ming.qian@xxxxxxxxxxx a écrit :
> > From: Ming Qian <ming.qian@xxxxxxxxxxx>
> >
> > The ADB in the VPUMIX domain has no separate reset and clock
> > enable bits, but is ungated and reset together with the VPUs.
> > So we can't reset G1 or G2 separately, it may led to the system hang.
> > Remove rst_mask and clk_mask of imx8mq_vpu_blk_ctl_domain_data.
> > Let imx8mq_vpu_power_notifier() do really vpu reset.
> >
> > Fixes: 608d7c325e85 ("soc: imx: imx8m-blk-ctrl: add i.MX8MQ VPU blk-ctrl")
> > Signed-off-by: Ming Qian <ming.qian@xxxxxxxxxxx>
> > ---
> >   drivers/pmdomain/imx/imx8m-blk-ctrl.c | 4 ----
> >   1 file changed, 4 deletions(-)
> >
> > diff --git a/drivers/pmdomain/imx/imx8m-blk-ctrl.c b/drivers/pmdomain/imx/imx8m-blk-ctrl.c
> > index 5c83e5599f1e..1f07ff041295 100644
> > --- a/drivers/pmdomain/imx/imx8m-blk-ctrl.c
> > +++ b/drivers/pmdomain/imx/imx8m-blk-ctrl.c
> > @@ -852,16 +852,12 @@ static const struct imx8m_blk_ctrl_domain_data imx8mq_vpu_blk_ctl_domain_data[]
> >   		.clk_names = (const char *[]){ "g1", },
> >   		.num_clks = 1,
> >   		.gpc_name = "g1",
> > -		.rst_mask = BIT(1),
> > -		.clk_mask = BIT(1),
> >   	},
> >   	[IMX8MQ_VPUBLK_PD_G2] = {
> >   		.name = "vpublk-g2",
> >   		.clk_names = (const char *[]){ "g2", },
> >   		.num_clks = 1,
> >   		.gpc_name = "g2",
> > -		.rst_mask = BIT(0),
> > -		.clk_mask = BIT(0),
> >   	},
>
> That was also our impression, but we could not get information about this HW.
> One question here, how do we ensure that we don't reset twice on power on ?
>
> Nicolas

The imx8mq_vpu_power_notifier() that is the power notifier callback of
imx8mq_vpu_blk_ctl_dev_data will do the real reset of G1 and G2.
	/*
	 * The ADB in the VPUMIX domain has no separate reset and clock
	 * enable bits, but is ungated and reset together with the VPUs. The
	 * reset and clock enable inputs to the ADB is a logical OR of the
	 * VPU bits. In order to set the G2 fuse bits, the G2 clock must
	 * also be enabled.
	 */
	regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(0) | BIT(1));
	regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(0) | BIT(1));

Thie notifier callback is set to bus power dev of vpu-blk-ctrl.

If we remove the reset mask from the G1/G2 blk-ctrl domain, then the VPU
is only set when the bus power domain power on.

I think the bus power domain can ensure that reset will not be executed
twice.

Regards,
Ming


> >   };
> >