RE: [PATCH RESEND v6 2/2] dmaengine: dw-edma: Add non-LL mode

[Verma, Devendra]

[AMD Official Use Only - AMD Internal Distribution Only]

Hi Eugen
Please check my response inline.

Regards,
Devendra

> -----Original Message-----
> From: Eugen Hristev <eugen.hristev@xxxxxxxxxx>
> Sent: Wednesday, December 3, 2025 2:54 PM
> To: Verma, Devendra <Devendra.Verma@xxxxxxx>; bhelgaas@xxxxxxxxxx;
> mani@xxxxxxxxxx; vkoul@xxxxxxxxxx
> Cc: dmaengine@xxxxxxxxxxxxxxx; linux-pci@xxxxxxxxxxxxxxx; linux-
> kernel@xxxxxxxxxxxxxxx; Simek, Michal <michal.simek@xxxxxxx>
> Subject: Re: [PATCH RESEND v6 2/2] dmaengine: dw-edma: Add non-LL mode
>
> Caution: This message originated from an External Source. Use proper
> caution when opening attachments, clicking links, or responding.
>
>
> On 12/1/25 11:58, Verma, Devendra wrote:
> > [AMD Official Use Only - AMD Internal Distribution Only]
> >
> > Hi All
> >
> > Could you all please review the following patch?
>
> No need to remind people, your patch will be reviewed.
>
> >
> > Regards,
> > Dev
> >
> >> -----Original Message-----
> >> From: Devendra K Verma <devendra.verma@xxxxxxx>
> >> Sent: Friday, November 21, 2025 5:05 PM
> >> To: bhelgaas@xxxxxxxxxx; mani@xxxxxxxxxx; vkoul@xxxxxxxxxx
> >> Cc: dmaengine@xxxxxxxxxxxxxxx; linux-pci@xxxxxxxxxxxxxxx; linux-
> >> kernel@xxxxxxxxxxxxxxx; Simek, Michal <michal.simek@xxxxxxx>; Verma,
> >> Devendra <Devendra.Verma@xxxxxxx>
> >> Subject: [PATCH RESEND v6 2/2] dmaengine: dw-edma: Add non-LL mode
> >>
> >> AMD MDB IP supports Linked List (LL) mode as well as non-LL mode.
>
> Is this non-LL mode some official name ? (e.g. in the datasheet or official
> product name ) Because having a 'bool non-LL' as false making it in a LL mode
> adds a double negation that is difficult to follow.

In the Designware databook for PCIe Express controller, provided by Synopsis, Linked List mode is referred to LL mode and non-LL mode where no Linked List is used. Hope this clarifies the doubt.

>  >> The current code does not have the mechanisms to enable the DMA
> >> transactions using the non-LL mode. The following two cases are added
> >> with this patch:
> >> - When a valid physical base address is not configured via the
> >>   Xilinx VSEC capability then the IP can still be used in non-LL
> >>   mode. The default mode for all the DMA transactions and for all
> >>   the DMA channels then is non-LL mode.
> >> - When a valid physical base address is configured but the client
> >>   wants to use the non-LL mode for DMA transactions then also the
> >>   flexibility is provided via the peripheral_config struct member of
> >>   dma_slave_config. In this case the channels can be individually
> >>   configured in non-LL mode. This use case is desirable for single
> >>   DMA transfer of a chunk, this saves the effort of preparing the
> >>   Link List. This particular scenario is applicable to AMD as well
> >>   as Synopsys IP.
> >>
> >> Signed-off-by: Devendra K Verma <devendra.verma@xxxxxxx>
>
> [...]