Re: [PATCH RESEND v6 2/2] dmaengine: dw-edma: Add non-LL mode

[Manivannan Sadhasivam]

On Thu, Dec 11, 2025 at 11:39:25AM +0000, Verma, Devendra wrote:
> [AMD Official Use Only - AMD Internal Distribution Only]
> 
> Hi Manivannan
> 
> > -----Original Message-----
> > From: Manivannan Sadhasivam <mani@xxxxxxxxxx>
> > Sent: Wednesday, December 10, 2025 6:59 PM
> > To: Verma, Devendra <Devendra.Verma@xxxxxxx>
> > Cc: bhelgaas@xxxxxxxxxx; vkoul@xxxxxxxxxx; dmaengine@xxxxxxxxxxxxxxx;
> > linux-pci@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; Simek, Michal
> > <michal.simek@xxxxxxx>
> > Subject: Re: [PATCH RESEND v6 2/2] dmaengine: dw-edma: Add non-LL mode
> >
> > Caution: This message originated from an External Source. Use proper caution
> > when opening attachments, clicking links, or responding.
> >
> >
> > On Wed, Dec 10, 2025 at 11:39:59AM +0000, Verma, Devendra wrote:
> > > [AMD Official Use Only - AMD Internal Distribution Only]
> > >
> > > Hi Manivannan
> > >
> > > Please check my response inline.
> > >
> > > Regards,
> > > Devendra
> > >
> > > > -----Original Message-----
> > > > From: Manivannan Sadhasivam <mani@xxxxxxxxxx>
> > > > Sent: Monday, December 8, 2025 11:00 AM
> > > > To: Verma, Devendra <Devendra.Verma@xxxxxxx>
> > > > Cc: bhelgaas@xxxxxxxxxx; vkoul@xxxxxxxxxx;
> > > > dmaengine@xxxxxxxxxxxxxxx; linux-pci@xxxxxxxxxxxxxxx;
> > > > linux-kernel@xxxxxxxxxxxxxxx; Simek, Michal <michal.simek@xxxxxxx>
> > > > Subject: Re: [PATCH RESEND v6 2/2] dmaengine: dw-edma: Add non-LL
> > > > mode
> > > >
> > > > Caution: This message originated from an External Source. Use proper
> > > > caution when opening attachments, clicking links, or responding.
> > > >
> > > >
> > > > On Fri, Nov 21, 2025 at 05:04:55PM +0530, Devendra K Verma wrote:
> > > > > AMD MDB IP supports Linked List (LL) mode as well as non-LL mode.
> > > > > The current code does not have the mechanisms to enable the DMA
> > > > > transactions using the non-LL mode. The following two cases are
> > > > > added with this patch:
> > > > > - When a valid physical base address is not configured via the
> > > > >   Xilinx VSEC capability then the IP can still be used in non-LL
> > > > >   mode. The default mode for all the DMA transactions and for all
> > > > >   the DMA channels then is non-LL mode.
> > > > > - When a valid physical base address is configured but the client
> > > > >   wants to use the non-LL mode for DMA transactions then also the
> > > > >   flexibility is provided via the peripheral_config struct member of
> > > > >   dma_slave_config. In this case the channels can be individually
> > > > >   configured in non-LL mode. This use case is desirable for single
> > > > >   DMA transfer of a chunk, this saves the effort of preparing the
> > > > >   Link List. This particular scenario is applicable to AMD as well
> > > > >   as Synopsys IP.
> > > > >
> > > >
> > > > Which in-kernel DMA client is using this non-LL mode?
> > > >
> > > > - Mani
> > > >
> > >
> > > Existing dma client application(s) can use the non-LL mode for the AMD
> > > (Xilinx) use case with the help of a simple peripheral_config variable
> > > which is part of the dma_slave_config structure.
> >
> > There is no existing client driver making use of this non-LL mode. So essentially,
> > this patch is introducing the dead code.
> >
> > > Though, no driver is using the non-LL mode as non-LL mode is not
> > > available in the current code.
> >
> > Then introduce non-LL mode when such client drivers start using it.
> >
> > - Mani
> >
> 
> Please excuse me as I left out a use case related to AMD MDB controller.
> The AMD MDB controller has a valid use-case for non-LL mode when the base physical
> address offset of the controller side DDR is not available / configured. In the absence
> of this offset the controller is not usable as the default mode enabled is LL mode.
> With the introduction of non-LL mode, if the offset is not configured then also controller
> can be used for the DMA transactions. The choice of non-LL or LL mode is use-case specific.
> The following snippet handles that scenario in the
> dw_edma_device_config() call:
> +     if (chan->dw->chip->non_ll || (!chan->dw->chip->non_ll && non_ll))
> +             chan->non_ll = true;
> 
> In my previous response, I explained that it is the optional configuration using which
> DMA clients can use the non-LL mode when the default mode used is LL mode.
> 
> I hope this clarifies, the code is not dead code rather it has use case for AMD MDB *and* an
> option to use non-LL mode for both Synopsys and AMD controller when LL mode is
> default mode. The default non-LL mode case is not available for Synopsys.
> 

Ok, thanks for clarification. If you've explained this in the commit message in
the first place, it would've helped me.

- Mani

-- 
மணிவண்ணன் சதாசிவம்