Re: [PATCH v7 05/10] nvmem: qcom-spmi-sdam: Migrate to devm_spmi_subdevice_alloc_and_add()

[AngeloGioacchino Del Regno]

Il 14/01/26 10:00, Andy Shevchenko ha scritto:
> On Wed, Jan 14, 2026 at 09:59:40AM +0100, AngeloGioacchino Del Regno wrote:
> > Il 14/01/26 09:56, Andy Shevchenko ha scritto:
> > > On Wed, Jan 14, 2026 at 09:39:52AM +0100, AngeloGioacchino Del Regno wrote:
> > > > Some Qualcomm PMICs integrate a SDAM device, internally located in
> > > > a specific address range reachable through SPMI communication.
> > > >
> > > > Instead of using the parent SPMI device (the main PMIC) as a kind
> > > > of syscon in this driver, register a new SPMI sub-device for SDAM
> > > > and initialize its own regmap with this sub-device's specific base
> > > > address, retrieved from the devicetree.
> > > >
> > > > This allows to stop manually adding the register base address to
> > > > every R/W call in this driver, as this can be, and is now, handled
> > > > by the regmap API instead.
>
> ...
>
> > > > +	struct regmap_config sdam_regmap_config = {
> > > > +		.reg_bits = 16,
> > > > +		.val_bits = 8,
> > >
> > > > +		.max_register = 0x100,
> > >
> > > Are you sure? This might be a bad naming, but here max == the last accessible.
> > > I bet it has to be 0xff (but since the address is 16-bit it might be actually
> > > 257 registers, but sounds very weird).
> >
> > Yes, I'm sure.
>
> So, what is resided on address 0x100 ?

I don't remember, this is research from around 5 months ago, when I've sent
the v1 of this.

If you really want though, I can incorrectly set max_register to 0xff.

Cheers,
Angelo

> > > > +		.fast_io = true,
> > > > +	};