Re: [PATCH v4 14/15] spi: cadence-qspi: Add support for the Renesas RZ/N1 controller

[Geert Uytterhoeven]

Hi Miquèl,

Thanks for your patch!

On Thu, 22 Jan 2026 at 16:14, Miquel Raynal (Schneider Electric)
<miquel.raynal@xxxxxxxxxxx> wrote:
> Renesas RZ/N1 QSPI controllers embed a modified version of the Cadence
> IP with the following settings:
> - a limited bus clock range
> - no DTR support
> - no DMA
> - no useful interrupt flag
> - only direct accesses (no INDAC mode)
> - write protection
>
> The controller has been tested by running the SPI NOR check list with a
> custom RZ/N1D400 based board mounted with a Spansion s25fl128s1 quad

"RZN1D-DB"?

> SPI.
>
> Tested-by: Wolfram Sang <wsa+renesas@xxxxxxxxxxxxxxxxxxxx>
> Signed-off-by: Miquel Raynal (Schneider Electric) <miquel.raynal@xxxxxxxxxxx>

> --- a/drivers/spi/spi-cadence-quadspi.c
> +++ b/drivers/spi/spi-cadence-quadspi.c
> @@ -110,6 +110,7 @@ struct cqspi_st {
>         bool                    apb_ahb_hazard;
>
>         bool                    is_jh7110; /* Flag for StarFive JH7110 SoC */
> +       bool                    is_rzn1; /* Flag for Renesas RZN1 SoC */

RZ/N1


>         bool                    disable_stig_mode;
>         refcount_t              refcount;
>         refcount_t              inflight_ops;

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds